pluto_hdl_adi/docs
AndreiGrozav 344ca6fc3d axi_pwm_gen: New features and fixes
New features:

1. External sync force the phase align. The external sync was used to align
   the phases of enabled pwms, but only after being armed by a
   load_config signal toggle.
   This feature lets the user decide between using load_config to
   arm and wait for a neg-edge of sync or automatic phase align trigger
   on the ext_sync neg-edge.
2. Force align. Lets the user chose between immediately stopping the
   active pulses and realigning them, or waiting for all running pulse
   periods end, before realigning.
3. Start at sync. When this feature is activated, the pulses will start immediately
   after the trigger event. Otherwise, each pulse will start after a period
   equal to the one for which it is set.
4. Use parameters to set the default status after reset of the
   - soft reset
   - start at sync
   - force align
   - ext sync align

Update regmap.

Fixes:

1. The polarity on disabled channels was staying high instead of low.
2. Fix 0 and 100 proc duty cycle configuration.

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
2024-04-19 15:23:55 +03:00
..
library docs: i3c_controller: Add documentation 2024-04-12 09:19:18 -03:00
projects Add pulsar_lvds project documentation 2024-04-16 11:40:31 +03:00
regmap axi_pwm_gen: New features and fixes 2024-04-19 15:23:55 +03:00
sources docs: Use doctools (#1258) 2024-02-22 11:32:04 -03:00
user_guide doc: Update hdl coding guidelines 2024-03-11 09:22:56 +02:00
Makefile docs: General improvements 2023-12-13 10:38:29 -03:00
conf.py docs: Use doctools (#1258) 2024-02-22 11:32:04 -03:00
index.rst docs: Use doctools (#1258) 2024-02-22 11:32:04 -03:00
make.bat docs: Include sphinx documentation 2023-09-27 14:36:34 -03:00
requirements.txt docs: Use doctools (#1258) 2024-02-22 11:32:04 -03:00