165 lines
6.1 KiB
Verilog
165 lines
6.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module avl_adxcfg (
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// reconfig sharing
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input rcfg_clk,
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input rcfg_reset_n,
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input rcfg_in_read_0,
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input rcfg_in_write_0,
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input [ 9:0] rcfg_in_address_0,
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input [31:0] rcfg_in_writedata_0,
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output [31:0] rcfg_in_readdata_0,
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output rcfg_in_waitrequest_0,
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input rcfg_in_read_1,
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input rcfg_in_write_1,
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input [ 9:0] rcfg_in_address_1,
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input [31:0] rcfg_in_writedata_1,
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output [31:0] rcfg_in_readdata_1,
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output rcfg_in_waitrequest_1,
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output rcfg_out_read_0,
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output rcfg_out_write_0,
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output [ 9:0] rcfg_out_address_0,
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output [31:0] rcfg_out_writedata_0,
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input [31:0] rcfg_out_readdata_0,
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input rcfg_out_waitrequest_0,
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output rcfg_out_read_1,
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output rcfg_out_write_1,
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output [ 9:0] rcfg_out_address_1,
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output [31:0] rcfg_out_writedata_1,
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input [31:0] rcfg_out_readdata_1,
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input rcfg_out_waitrequest_1);
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// internal registers
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reg [ 1:0] rcfg_select = 'd0;
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reg rcfg_read_int = 'd0;
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reg rcfg_write_int = 'd0;
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reg [ 9:0] rcfg_address_int = 'd0;
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reg [31:0] rcfg_writedata_int = 'd0;
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reg [31:0] rcfg_readdata_int = 'd0;
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reg rcfg_waitrequest_int_0 = 'd1;
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reg rcfg_waitrequest_int_1 = 'd1;
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// internal signals
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wire [31:0] rcfg_readdata_s;
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wire rcfg_waitrequest_s;
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// xcvr sharing requires same bus (sw must make sure they are mutually exclusive access).
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assign rcfg_out_read_0 = rcfg_read_int;
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assign rcfg_out_write_0 = rcfg_write_int;
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assign rcfg_out_address_0 = rcfg_address_int;
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assign rcfg_out_writedata_0 = rcfg_writedata_int;
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assign rcfg_out_read_1 = rcfg_read_int;
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assign rcfg_out_write_1 = rcfg_write_int;
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assign rcfg_out_address_1 = rcfg_address_int;
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assign rcfg_out_writedata_1 = rcfg_writedata_int;
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assign rcfg_in_readdata_0 = rcfg_readdata_int;
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assign rcfg_in_readdata_1 = rcfg_readdata_int;
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assign rcfg_in_waitrequest_0 = rcfg_waitrequest_int_0;
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assign rcfg_in_waitrequest_1 = rcfg_waitrequest_int_1;
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assign rcfg_readdata_s = rcfg_out_readdata_1 & rcfg_out_readdata_0;
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assign rcfg_waitrequest_s = rcfg_out_waitrequest_1 & rcfg_out_waitrequest_0;
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always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
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if (rcfg_reset_n == 0) begin
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rcfg_select <= 2'd0;
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rcfg_read_int <= 1'd0;
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rcfg_write_int <= 1'd0;
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rcfg_address_int <= 10'd0;
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rcfg_writedata_int <= 32'd0;
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rcfg_readdata_int <= 32'd0;
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rcfg_waitrequest_int_0 <= 1'b1;
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rcfg_waitrequest_int_1 <= 1'b1;
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end else begin
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if (rcfg_select[1] == 1'b1) begin
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if (rcfg_waitrequest_s == 1'b0) begin
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rcfg_select <= 2'd0;
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rcfg_read_int <= 1'b0;
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rcfg_write_int <= 1'b0;
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rcfg_address_int <= 10'd0;
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rcfg_writedata_int <= 32'd0;
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end
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rcfg_readdata_int <= rcfg_readdata_s;
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rcfg_waitrequest_int_0 <= rcfg_waitrequest_s | rcfg_select[0];
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rcfg_waitrequest_int_1 <= rcfg_waitrequest_s | ~rcfg_select[0];
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end else if ((rcfg_in_read_0 == 1'b1) || (rcfg_in_write_0 == 1'b1)) begin
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rcfg_select <= 2'b10;
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rcfg_read_int <= rcfg_in_read_0;
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rcfg_write_int <= rcfg_in_write_0;
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rcfg_address_int <= rcfg_in_address_0;
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rcfg_writedata_int <= rcfg_in_writedata_0;
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rcfg_readdata_int <= 32'd0;
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rcfg_waitrequest_int_0 <= 1'b1;
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rcfg_waitrequest_int_1 <= 1'b1;
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end else if ((rcfg_in_read_1 == 1'b1) || (rcfg_in_write_1 == 1'b1)) begin
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rcfg_select <= 2'b11;
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rcfg_read_int <= rcfg_in_read_1;
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rcfg_write_int <= rcfg_in_write_1;
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rcfg_address_int <= rcfg_in_address_1;
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rcfg_writedata_int <= rcfg_in_writedata_1;
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rcfg_readdata_int <= 32'd0;
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rcfg_waitrequest_int_0 <= 1'b1;
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rcfg_waitrequest_int_1 <= 1'b1;
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end else begin
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rcfg_select <= 2'd0;
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rcfg_read_int <= 1'd0;
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rcfg_write_int <= 1'd0;
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rcfg_address_int <= 10'd0;
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rcfg_writedata_int <= 32'd0;
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rcfg_readdata_int <= 32'd0;
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rcfg_waitrequest_int_0 <= 1'b1;
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rcfg_waitrequest_int_1 <= 1'b1;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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