298 lines
8.2 KiB
Verilog
298 lines
8.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9379_tx #(
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parameter DATAPATH_DISABLE = 0,
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parameter ID = 0) (
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// dac interface
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output dac_rst,
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input dac_clk,
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output [127:0] dac_data,
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// master/slave
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input dac_sync_in,
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output dac_sync_out,
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// dma interface
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output dac_enable_i0,
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output dac_valid_i0,
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input [ 31:0] dac_data_i0,
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output dac_enable_q0,
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output dac_valid_q0,
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input [ 31:0] dac_data_q0,
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output dac_enable_i1,
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output dac_valid_i1,
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input [ 31:0] dac_data_i1,
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output dac_enable_q1,
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output dac_valid_q1,
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input [ 31:0] dac_data_q1,
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input dac_dovf,
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input dac_dunf,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [ 13:0] up_waddr,
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input [ 31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [ 13:0] up_raddr,
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output reg [ 31:0] up_rdata,
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output reg up_rack);
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// internal registers
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reg dac_data_sync = 'd0;
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// internal signals
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wire dac_data_sync_s;
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wire [ 31:0] dac_data_iq_i0_s;
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wire [ 31:0] dac_data_iq_q0_s;
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wire [ 31:0] dac_data_iq_i1_s;
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wire [ 31:0] dac_data_iq_q1_s;
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wire dac_dds_format_s;
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wire [ 4:0] up_wack_s;
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wire [ 4:0] up_rack_s;
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wire [ 31:0] up_rdata_s[0:4];
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// master/slave
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assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
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always @(posedge dac_clk) begin
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dac_data_sync <= dac_data_sync_s;
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_wack <= | up_wack_s;
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up_rack <= | up_rack_s;
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
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up_rdata_s[3] | up_rdata_s[4];
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end
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end
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// dac channel
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assign dac_valid_i0 = 1'b1;
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axi_ad9379_tx_channel #(
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.CHANNEL_ID (0),
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.Q_OR_I_N (0),
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.DATAPATH_DISABLE (DATAPATH_DISABLE))
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i_tx_channel_0 (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data_in (dac_data_i0),
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.dac_data_out (dac_data[31:0]),
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.dac_data_iq_in (dac_data_iq_q0_s),
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.dac_data_iq_out (dac_data_iq_i0_s),
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.dac_enable (dac_enable_i0),
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.dac_data_sync (dac_data_sync),
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.dac_dds_format (dac_dds_format_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[0]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[0]),
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.up_rack (up_rack_s[0]));
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// dac channel
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assign dac_valid_q0 = 1'b1;
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axi_ad9379_tx_channel #(
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.CHANNEL_ID (1),
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.Q_OR_I_N (1),
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.DATAPATH_DISABLE (DATAPATH_DISABLE))
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i_tx_channel_1 (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data_in (dac_data_q0),
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.dac_data_out (dac_data[63:32]),
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.dac_data_iq_in (dac_data_iq_i0_s),
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.dac_data_iq_out (dac_data_iq_q0_s),
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.dac_enable (dac_enable_q0),
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.dac_data_sync (dac_data_sync),
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.dac_dds_format (dac_dds_format_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[1]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[1]),
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.up_rack (up_rack_s[1]));
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// dac channel
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assign dac_valid_i1 = 1'b1;
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axi_ad9379_tx_channel #(
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.CHANNEL_ID (2),
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.Q_OR_I_N (0),
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.DATAPATH_DISABLE (DATAPATH_DISABLE))
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i_tx_channel_2 (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data_in (dac_data_i1),
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.dac_data_out (dac_data[95:64]),
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.dac_data_iq_in (dac_data_iq_q1_s),
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.dac_data_iq_out (dac_data_iq_i1_s),
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.dac_enable (dac_enable_i1),
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.dac_data_sync (dac_data_sync),
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.dac_dds_format (dac_dds_format_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[2]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[2]),
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.up_rack (up_rack_s[2]));
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// dac channel
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assign dac_valid_q1 = 1'b1;
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axi_ad9379_tx_channel #(
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.CHANNEL_ID (3),
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.Q_OR_I_N (1),
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.DATAPATH_DISABLE (DATAPATH_DISABLE))
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i_tx_channel_3 (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data_in (dac_data_q1),
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.dac_data_out (dac_data[127:96]),
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.dac_data_iq_in (dac_data_iq_i1_s),
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.dac_data_iq_out (dac_data_iq_q1_s),
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.dac_enable (dac_enable_q1),
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.dac_data_sync (dac_data_sync),
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.dac_dds_format (dac_dds_format_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[3]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[3]),
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.up_rack (up_rack_s[3]));
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// dac common processor interface
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up_dac_common #(
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.ID (ID),
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.CONFIG(0),
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.CLK_EDGE_SEL(0),
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.COMMON_ID(6'h10),
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.DRP_DISABLE(1),
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.USERPORTS_DISABLE(1),
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.GPIO_DISABLE(1))
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i_up_dac_common (
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.mmcm_rst (),
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_sync (dac_sync_out),
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.dac_frame (),
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.dac_clksel (),
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.dac_par_type (),
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.dac_par_enb (),
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.dac_r1_mode (),
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.dac_datafmt (dac_dds_format_s),
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.dac_datarate (),
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.dac_status (1'b1),
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.dac_status_ovf (dac_dovf),
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.dac_status_unf (dac_dunf),
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.dac_clk_ratio (32'd2),
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.up_dac_ce (),
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.up_pps_rcounter(32'h0),
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.up_pps_status(1'b0),
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.up_pps_irq_mask(),
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.up_drp_sel (),
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.up_drp_wr (),
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.up_drp_addr (),
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.up_drp_wdata (),
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.up_drp_rdata (32'd0),
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.up_drp_ready (1'd0),
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.up_drp_locked (1'd1),
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.up_usr_chanmax (),
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.dac_usr_chanmax (8'd3),
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.up_dac_gpio_in (32'd0),
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.up_dac_gpio_out (),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[4]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[4]),
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.up_rack (up_rack_s[4]));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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