517 lines
16 KiB
Verilog
517 lines
16 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This interface includes both the transmit and receive components -
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// They both uses the same clock (sourced from the receiving side).
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`timescale 1ns/100ps
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module axi_ad9361_dev_if (
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// physical interface (receive)
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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// physical interface (transmit)
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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// clock (common to both receive and transmit)
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rst,
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clk,
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l_clk,
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// receive data path interface
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adc_valid,
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adc_data,
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adc_status,
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adc_r1_mode,
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// transmit data path interface
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dac_valid,
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dac_data,
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dac_r1_mode,
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// delay control signals
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delay_clk,
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delay_rst,
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delay_sel,
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delay_rwn,
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delay_addr,
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delay_wdata,
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delay_rdata,
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delay_ack_t,
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delay_locked,
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// chipscope signals
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dev_dbg_data,
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dev_l_dbg_data);
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// this parameter controls the buffer type based on the target device.
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parameter PCORE_DEVICE_TYPE = 0;
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parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
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localparam PCORE_7SERIES = 0;
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localparam PCORE_VIRTEX6 = 1;
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// physical interface (receive)
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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// physical interface (transmit)
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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// clock (common to both receive and transmit)
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input rst;
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input clk;
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output l_clk;
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// receive data path interface
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output adc_valid;
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output [47:0] adc_data;
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output adc_status;
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input adc_r1_mode;
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// transmit data path interface
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input dac_valid;
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input [47:0] dac_data;
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input dac_r1_mode;
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// delay control signals
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input delay_clk;
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input delay_rst;
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input delay_sel;
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input delay_rwn;
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input [ 7:0] delay_addr;
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input [ 4:0] delay_wdata;
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output [ 4:0] delay_rdata;
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output delay_ack_t;
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output delay_locked;
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// chipscope signals
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output [111:0] dev_dbg_data;
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output [ 61:0] dev_l_dbg_data;
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// internal registers
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reg [11:0] rx_data = 'd0;
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reg [ 1:0] rx_frame = 'd0;
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reg [11:0] rx_data_d = 'd0;
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reg [ 1:0] rx_frame_d = 'd0;
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reg rx_error_r1 = 'd0;
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reg rx_valid_r1 = 'd0;
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reg [23:0] rx_data_r1 = 'd0;
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reg rx_error_r2 = 'd0;
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reg rx_valid_r2 = 'd0;
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reg [47:0] rx_data_r2 = 'd0;
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reg adc_p_valid = 'd0;
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reg [47:0] adc_p_data = 'd0;
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reg adc_p_status = 'd0;
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reg adc_n_valid = 'd0;
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reg [47:0] adc_n_data = 'd0;
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reg adc_n_status = 'd0;
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reg adc_valid_int = 'd0;
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reg [47:0] adc_data_int = 'd0;
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reg adc_status_int = 'd0;
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reg adc_valid = 'd0;
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reg [47:0] adc_data = 'd0;
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reg adc_status = 'd0;
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reg [ 2:0] tx_data_cnt = 'd0;
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reg [47:0] tx_data = 'd0;
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reg tx_frame = 'd0;
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reg [ 5:0] tx_data_p = 'd0;
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reg [ 5:0] tx_data_n = 'd0;
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reg tx_n_frame = 'd0;
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reg [ 5:0] tx_n_data_p = 'd0;
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reg [ 5:0] tx_n_data_n = 'd0;
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reg tx_p_frame = 'd0;
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reg [ 5:0] tx_p_data_p = 'd0;
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reg [ 5:0] tx_p_data_n = 'd0;
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reg [ 6:0] delay_ld = 'd0;
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reg [ 4:0] delay_rdata = 'd0;
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reg delay_ack_t = 'd0;
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// internal signals
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wire [ 3:0] rx_frame_s;
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wire [ 3:0] tx_data_sel_s;
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wire [ 4:0] delay_rdata_s[6:0];
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wire [ 5:0] rx_data_p_s;
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wire [ 5:0] rx_data_n_s;
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wire rx_frame_p_s;
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wire rx_frame_n_s;
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genvar l_inst;
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// device debug signals
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assign dev_dbg_data[ 5: 0] = tx_data_n;
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assign dev_dbg_data[ 11: 6] = tx_data_p;
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assign dev_dbg_data[ 23: 12] = dac_data[11: 0];
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assign dev_dbg_data[ 35: 24] = dac_data[23:12];
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assign dev_dbg_data[ 47: 36] = dac_data[35:24];
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assign dev_dbg_data[ 59: 48] = dac_data[47:36];
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assign dev_dbg_data[ 71: 60] = adc_data[11: 0];
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assign dev_dbg_data[ 83: 72] = adc_data[23:12];
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assign dev_dbg_data[ 95: 84] = adc_data[35:24];
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assign dev_dbg_data[107: 96] = adc_data[47:36];
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assign dev_dbg_data[108:108] = tx_frame;
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assign dev_dbg_data[109:109] = dac_valid;
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assign dev_dbg_data[110:110] = adc_status;
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assign dev_dbg_data[111:111] = adc_valid;
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assign dev_l_dbg_data[ 5: 0] = tx_p_data_n;
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assign dev_l_dbg_data[ 11: 6] = tx_p_data_p;
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assign dev_l_dbg_data[ 23: 12] = adc_p_data[11: 0];
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assign dev_l_dbg_data[ 35: 24] = adc_p_data[23:12];
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assign dev_l_dbg_data[ 47: 36] = adc_p_data[35:24];
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assign dev_l_dbg_data[ 59: 48] = adc_p_data[47:36];
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assign dev_l_dbg_data[ 60: 60] = tx_p_frame;
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assign dev_l_dbg_data[ 61: 61] = adc_p_valid;
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// receive data path interface
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assign rx_frame_s = {rx_frame_d, rx_frame};
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always @(posedge l_clk) begin
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rx_data <= {rx_data_n_s, rx_data_p_s};
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rx_frame <= {rx_frame_n_s, rx_frame_p_s};
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rx_data_d <= rx_data;
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rx_frame_d <= rx_frame;
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end
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// receive data path for single rf, frame is expected to qualify i/q msb only
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always @(posedge l_clk) begin
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rx_error_r1 <= ((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
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rx_valid_r1 <= (rx_frame_s == 4'b1100) ? 1'b1 : 1'b0;
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if (rx_frame_s == 4'b1100) begin
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rx_data_r1[11: 0] <= {rx_data_d[11:6], rx_data[11:6]};
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rx_data_r1[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
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end
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end
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// receive data path for dual rf, frame is expected to qualify i/q msb and lsb for rf-1 only
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always @(posedge l_clk) begin
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rx_error_r2 <= ((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) ||
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(rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
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rx_valid_r2 <= (rx_frame_s == 4'b0000) ? 1'b1 : 1'b0;
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if (rx_frame_s == 4'b1111) begin
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rx_data_r2[11: 0] <= {rx_data_d[11:6], rx_data[11:6]};
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rx_data_r2[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
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end
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if (rx_frame_s == 4'b0000) begin
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rx_data_r2[35:24] <= {rx_data_d[11:6], rx_data[11:6]};
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rx_data_r2[47:36] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
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end
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end
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// receive data path mux
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always @(posedge l_clk) begin
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if (adc_r1_mode == 1'b1) begin
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adc_p_valid <= rx_valid_r1;
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adc_p_data <= {24'd0, rx_data_r1};
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adc_p_status <= ~rx_error_r1;
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end else begin
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adc_p_valid <= rx_valid_r2;
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adc_p_data <= rx_data_r2;
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adc_p_status <= ~rx_error_r2;
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end
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end
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// transfer to a synchronous common clock
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always @(negedge l_clk) begin
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adc_n_valid <= adc_p_valid;
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adc_n_data <= adc_p_data;
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adc_n_status <= adc_p_status;
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end
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always @(posedge clk) begin
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adc_valid_int <= adc_n_valid;
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adc_data_int <= adc_n_data;
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adc_status_int <= adc_n_status;
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adc_valid <= adc_valid_int;
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if (adc_valid_int == 1'b1) begin
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adc_data <= adc_data_int;
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end
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adc_status <= adc_status_int;
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end
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// transmit data path mux (reverse of what receive does above)
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// the count simply selets the data muxing on the ddr outputs
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assign tx_data_sel_s = {tx_data_cnt[2], dac_r1_mode, tx_data_cnt[1:0]};
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always @(posedge clk) begin
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if (dac_valid == 1'b1) begin
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tx_data_cnt <= 3'b100;
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end else if (tx_data_cnt[2] == 1'b1) begin
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tx_data_cnt <= tx_data_cnt + 1'b1;
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end
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if (dac_valid == 1'b1) begin
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tx_data <= dac_data;
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end
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case (tx_data_sel_s)
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4'b1111: begin
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tx_frame <= 1'b0;
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tx_data_p <= tx_data[ 5: 0];
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tx_data_n <= tx_data[17:12];
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end
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4'b1110: begin
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tx_frame <= 1'b1;
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tx_data_p <= tx_data[11: 6];
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tx_data_n <= tx_data[23:18];
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end
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4'b1101: begin
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tx_frame <= 1'b0;
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tx_data_p <= tx_data[ 5: 0];
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tx_data_n <= tx_data[17:12];
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end
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4'b1100: begin
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tx_frame <= 1'b1;
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tx_data_p <= tx_data[11: 6];
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tx_data_n <= tx_data[23:18];
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end
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4'b1011: begin
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tx_frame <= 1'b0;
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tx_data_p <= tx_data[29:24];
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tx_data_n <= tx_data[41:36];
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end
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4'b1010: begin
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tx_frame <= 1'b0;
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tx_data_p <= tx_data[35:30];
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tx_data_n <= tx_data[47:42];
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end
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4'b1001: begin
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tx_frame <= 1'b1;
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tx_data_p <= tx_data[ 5: 0];
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tx_data_n <= tx_data[17:12];
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end
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4'b1000: begin
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tx_frame <= 1'b1;
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tx_data_p <= tx_data[11: 6];
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tx_data_n <= tx_data[23:18];
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end
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default: begin
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tx_frame <= 1'b0;
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tx_data_p <= 6'd0;
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tx_data_n <= 6'd0;
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end
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endcase
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end
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// transfer data from a synchronous clock (skew less than 2ns)
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always @(negedge clk) begin
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tx_n_frame <= tx_frame;
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tx_n_data_p <= tx_data_p;
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tx_n_data_n <= tx_data_n;
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end
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always @(posedge l_clk) begin
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tx_p_frame <= tx_n_frame;
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tx_p_data_p <= tx_n_data_p;
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tx_p_data_n <= tx_n_data_n;
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end
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// delay write interface, each delay element can be individually
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// addressed, and a delay value can be directly loaded (no inc/dec stuff)
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always @(posedge delay_clk) begin
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if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
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case (delay_addr)
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8'h06: delay_ld <= 7'h40;
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8'h05: delay_ld <= 7'h20;
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8'h04: delay_ld <= 7'h10;
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8'h03: delay_ld <= 7'h08;
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8'h02: delay_ld <= 7'h04;
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8'h01: delay_ld <= 7'h02;
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8'h00: delay_ld <= 7'h01;
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default: delay_ld <= 7'h00;
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endcase
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end else begin
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delay_ld <= 7'h00;
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end
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end
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// delay read interface, a delay ack toggle is used to transfer data to the
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// processor side- delay locked is independently transferred
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always @(posedge delay_clk) begin
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case (delay_addr)
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8'h06: delay_rdata <= delay_rdata_s[6];
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8'h05: delay_rdata <= delay_rdata_s[5];
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8'h04: delay_rdata <= delay_rdata_s[4];
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8'h03: delay_rdata <= delay_rdata_s[3];
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8'h02: delay_rdata <= delay_rdata_s[2];
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8'h01: delay_rdata <= delay_rdata_s[1];
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8'h00: delay_rdata <= delay_rdata_s[0];
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default: delay_rdata <= 5'd0;
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endcase
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if (delay_sel == 1'b1) begin
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delay_ack_t <= ~delay_ack_t;
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end
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end
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// receive data interface, ibuf -> idelay -> iddr
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generate
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for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_rx_data
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ad_lvds_in #(
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.BUFTYPE (PCORE_DEVICE_TYPE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (PCORE_IODELAY_GROUP))
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i_rx_data (
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.rx_clk (l_clk),
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.rx_data_in_p (rx_data_in_p[l_inst]),
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.rx_data_in_n (rx_data_in_n[l_inst]),
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.rx_data_p (rx_data_p_s[l_inst]),
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.rx_data_n (rx_data_n_s[l_inst]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_ld (delay_ld[l_inst]),
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.delay_wdata (delay_wdata),
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.delay_rdata (delay_rdata_s[l_inst]),
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.delay_locked ());
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end
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endgenerate
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// receive frame interface, ibuf -> idelay -> iddr
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ad_lvds_in #(
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.BUFTYPE (PCORE_DEVICE_TYPE),
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.IODELAY_CTRL (1),
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.IODELAY_GROUP (PCORE_IODELAY_GROUP))
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i_rx_frame (
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.rx_clk (l_clk),
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.rx_data_in_p (rx_frame_in_p),
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.rx_data_in_n (rx_frame_in_n),
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.rx_data_p (rx_frame_p_s),
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.rx_data_n (rx_frame_n_s),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_ld (delay_ld[6]),
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.delay_wdata (delay_wdata),
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.delay_rdata (delay_rdata_s[6]),
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.delay_locked (delay_locked));
|
|
|
|
// transmit data interface, oddr -> obuf
|
|
|
|
generate
|
|
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data
|
|
ad_lvds_out #(
|
|
.BUFTYPE (PCORE_DEVICE_TYPE))
|
|
i_tx_data (
|
|
.tx_clk (l_clk),
|
|
.tx_data_p (tx_p_data_p[l_inst]),
|
|
.tx_data_n (tx_p_data_n[l_inst]),
|
|
.tx_data_out_p (tx_data_out_p[l_inst]),
|
|
.tx_data_out_n (tx_data_out_n[l_inst]));
|
|
end
|
|
endgenerate
|
|
|
|
// transmit frame interface, oddr -> obuf
|
|
|
|
ad_lvds_out #(
|
|
.BUFTYPE (PCORE_DEVICE_TYPE))
|
|
i_tx_frame (
|
|
.tx_clk (l_clk),
|
|
.tx_data_p (tx_p_frame),
|
|
.tx_data_n (tx_p_frame),
|
|
.tx_data_out_p (tx_frame_out_p),
|
|
.tx_data_out_n (tx_frame_out_n));
|
|
|
|
// transmit clock interface, oddr -> obuf
|
|
|
|
ad_lvds_out #(
|
|
.BUFTYPE (PCORE_DEVICE_TYPE))
|
|
i_tx_clk (
|
|
.tx_clk (l_clk),
|
|
.tx_data_p (1'b0),
|
|
.tx_data_n (1'b1),
|
|
.tx_data_out_p (tx_clk_out_p),
|
|
.tx_data_out_n (tx_clk_out_n));
|
|
|
|
// device clock interface (receive clock)
|
|
|
|
ad_lvds_clk #(
|
|
.BUFTYPE (PCORE_DEVICE_TYPE))
|
|
i_clk (
|
|
.clk_in_p (rx_clk_in_p),
|
|
.clk_in_n (rx_clk_in_n),
|
|
.clk (l_clk));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|