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Istvan Csomortani 34ffa15b12 zynq_plddr3: Fix PLDDR3's Reset Generator 
Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset.
Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to
set this two property of the reset generator.
 		2014-12-04 15:39:17 +02:00
library up_axi: Fix up_raddr/up_waddr port width 2014-12-01 13:22:28 +01:00
projects zynq_plddr3: Fix PLDDR3's Reset Generator 2014-12-04 15:39:17 +02:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Add a link to EngineerZone 2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga