3516c4ca83
For most of the ADCs that use JESD204 as the data transport the digitial interface is very similar. They are mainly differentiated by number of JESD204 lanes, number of converter channels and number of bits per sample. Currently for each supported converter there exists a converter specific core which has the converter specific requirements hard-coded. Introduce a new generic core that has the number of lanes, number of channels and bits per sample as synthesis-time configurable parameters. It can be used as a drop-in replacement for the existing converter specific cores. This has the advantage of a shared and reduced code base. Code improvements will automatically be available for all converters and don't have to be manually ported to each core individually. It also makes it very easy to introduce support for new converters that follow the existing schema. Since the JESD204 deframer is now procedurally generated it is also very easy to support board or application specific requirements where the lane to converter ratio differs from the default (E.g. use 2 lanes/2 converters instead of 4 lanes/2 converters). This new core is primarily based on the existing axi_ad9680. For the time being the core is not user instantiatable and will only be used as a based to re-implement the converter specific cores. It will be extended in the future to allow user instantiation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects.
Getting started
This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.
Prerequisites
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Please make sure that you have the required tool version.
How to build a project
For building a projects, you have to use the GNU Make tool. If you're a Windows user please checkout this page, to see how you can install this tool.
To build a project, checkout the latest release, after that just cd to the project that you want to build and run make:
[~]cd projects/fmcomms2/zc706
[~]make
A more comprehensive build guide can be found under the following link: https://wiki.analog.com/resources/fpga/docs/build
Software
In general all the projects have no-OS (baremetal) and a Linux support. See no-OS or Linux for more information.
Which branch should I use?
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If you want to use the most stable code base, always use the latest release branch.
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If you want to use the greatest and latest, check out the master branch.
License
In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.
The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.
See LICENSE for more details. The separate license files cab be found here:
Comprehensive user guide
See HDL User Guide for a more detailed guide.
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