223 lines
6.4 KiB
Verilog
223 lines
6.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9684_if #(
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parameter DEVICE_TYPE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group",
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parameter OR_STATUS = 0) (
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// device interface
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input adc_clk_in_p,
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input adc_clk_in_n,
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input [13:0] adc_data_in_p,
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input [13:0] adc_data_in_n,
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input adc_data_or_p,
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input adc_data_or_n,
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// data interface
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output adc_clk,
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input adc_rst,
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output [27:0] adc_data_a,
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output adc_or_a,
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output [27:0] adc_data_b,
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output adc_or_b,
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output reg adc_status,
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// delay interface
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input delay_clk,
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input delay_rst,
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input [14:0] delay_dload,
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input [74:0] delay_wdata,
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output [74:0] delay_rdata,
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output delay_locked,
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// reset
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input rst,
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// drp interface
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input up_clk,
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input up_rstn,
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input up_drp_sel,
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input up_drp_wr,
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input [11:0] up_drp_addr,
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input [31:0] up_drp_wdata,
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output [31:0] up_drp_rdata,
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output up_drp_ready,
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output up_drp_locked);
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localparam DDR_OR_SDR_N = 1;
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// internal registers
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reg adc_status_m1 = 'd0;
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// internal signals
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wire adc_clk_in;
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wire adc_div_clk;
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wire [ 1:0] adc_data_or_a_s;
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wire [ 1:0] adc_data_or_b_s;
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wire loaden_s;
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wire [ 7:0] phase_s;
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genvar l_inst;
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// adc_clk is 1:2 of the sampling clock
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// f_max = 250 MHz
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assign adc_clk = adc_div_clk;
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// data interface
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ad_serdes_in #(
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.DEVICE_TYPE(DEVICE_TYPE),
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.IODELAY_CTRL(1),
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.IODELAY_GROUP(IO_DELAY_GROUP),
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.DDR_OR_SDR_N(DDR_OR_SDR_N),
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.DATA_WIDTH(14))
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i_adc_data (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.loaden(loaden_s),
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.phase(phase_s),
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.locked(1'b0),
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.data_s0(adc_data_b[27:14]),
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.data_s1(adc_data_a[27:14]),
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.data_s2(adc_data_b[13: 0]),
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.data_s3(adc_data_a[13: 0]),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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.data_s7(),
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.data_in_p(adc_data_in_p[13:0]),
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.data_in_n(adc_data_in_n[13:0]),
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.up_clk (up_clk),
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.up_dld (delay_dload[13:0]),
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.up_dwdata (delay_wdata[69:0]),
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.up_drdata (delay_rdata[69:0]),
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.delay_clk(delay_clk),
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.delay_rst(delay_rst),
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.delay_locked(delay_locked));
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generate if (OR_STATUS == 1) begin
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ad_serdes_in #(
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.DEVICE_TYPE(DEVICE_TYPE),
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.IODELAY_CTRL(0),
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.IODELAY_GROUP(IO_DELAY_GROUP),
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.DDR_OR_SDR_N(DDR_OR_SDR_N),
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.DATA_WIDTH(1))
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i_adc_or (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.loaden(loaden_s),
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.phase(phase_s),
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.locked(1'b0),
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.data_s0(adc_data_or_b_s[1]),
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.data_s1(adc_data_or_a_s[1]),
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.data_s2(adc_data_or_b_s[0]),
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.data_s3(adc_data_or_a_s[0]),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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.data_s7(),
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.data_in_p(adc_data_or_p),
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.data_in_n(adc_data_or_n),
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.up_clk (up_clk),
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.up_dld (delay_dload[14]),
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.up_dwdata (delay_wdata[74:70]),
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.up_drdata (delay_rdata[74:70]),
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.delay_clk(delay_clk),
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.delay_rst(delay_rst),
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.delay_locked());
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assign adc_or_a = adc_data_or_a_s[0] | adc_data_or_a_s[1];
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assign adc_or_b = adc_data_or_b_s[0] | adc_data_or_b_s[1];
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end else begin
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assign adc_or_a = 1'b0;
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assign adc_or_b = 1'b0;
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end
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endgenerate
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// clock input buffers and MMCM_OR_BUFR_N
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ad_serdes_clk #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.MMCM_CLKIN_PERIOD (2),
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.MMCM_VCO_DIV (6),
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.MMCM_VCO_MUL (12),
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.MMCM_CLK0_DIV (2),
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.MMCM_CLK1_DIV (4))
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i_serdes_clk (
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.rst (rst),
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.clk_in_p (adc_clk_in_p),
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.clk_in_n (adc_clk_in_n),
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.clk (adc_clk_in),
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.div_clk (adc_div_clk),
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.out_clk (),
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.loaden (loaden_s),
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.phase (phase_s),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_drp_sel (up_drp_sel),
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.up_drp_wr (up_drp_wr),
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.up_drp_addr (up_drp_addr),
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.up_drp_wdata (up_drp_wdata),
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.up_drp_rdata (up_drp_rdata),
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.up_drp_ready (up_drp_ready),
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.up_drp_locked (up_drp_locked));
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// adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up
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always @(posedge adc_div_clk) begin
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if(adc_rst == 1'b1) begin
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adc_status_m1 <= 1'b0;
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adc_status <= 1'b0;
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end else begin
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adc_status_m1 <= up_drp_locked;
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adc_status <= adc_status_m1;
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end
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end
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endmodule
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