94 lines
2.8 KiB
Verilog
94 lines
2.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module response_handler #(
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parameter ID_WIDTH = 3)(
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input clk,
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input resetn,
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input bvalid,
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output bready,
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input [1:0] bresp,
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output reg [ID_WIDTH-1:0] id,
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input [ID_WIDTH-1:0] request_id,
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input enable,
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output reg enabled,
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input eot,
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output resp_valid,
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input resp_ready,
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output resp_eot,
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output [1:0] resp_resp
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);
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`include "resp.vh"
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`include "inc_id.vh"
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assign resp_resp = bresp;
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assign resp_eot = eot;
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wire active = id != request_id;
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assign bready = active && resp_ready;
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assign resp_valid = active && bvalid;
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// We have to wait for all responses before we can disable the response handler
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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enabled <= 1'b0;
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end else if (enable == 1'b1) begin
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enabled <= 1'b1;
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end else if (request_id == id) begin
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enabled <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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id <= 'h0;
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end else if (bready == 1'b1 && bvalid == 1'b1) begin
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id <= inc_id(id);
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end
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end
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endmodule
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