41 lines
2.0 KiB
Plaintext
41 lines
2.0 KiB
Plaintext
# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
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# more information. This commercial license is sub-licensable (if you purchase
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# chips from Analog Devices, incorporate them into your PCB level product, and
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# purchase a JESD204 license, end users of your product will also have a
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
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# or publication in which you use this JESD204 HDL core. (You are not required
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# to do so; it is up to your common sense to decide whether you want to comply
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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<: setFileUsedIn { out_of_context synthesis implementation } :>
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<: ;#Component and file information :>
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<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./" :>
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<: setFileName $ComponentName :>
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<: setFileExtension "_ooc.xdc" :>
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# This XDC is used only for OOC mode of synthesis, implementation.
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# These are default values for timing driven synthesis during OOC flow.
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# These values will be overwritten during implementation with information
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# from top level.
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create_clock -name clk -period 2.5 [get_ports clk]
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create_clock -name device_clk -period 2.5 [get_ports device_clk]
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################################################################################
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