318 lines
9.5 KiB
Verilog
318 lines
9.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input sys_rst,
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input sys_clk_p,
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input sys_clk_n,
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input uart_sin,
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output uart_sout,
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output [ 2:0] ddr3_1_n,
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output [ 1:0] ddr3_1_p,
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output ddr3_reset_n,
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output [13:0] ddr3_addr,
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output [ 2:0] ddr3_ba,
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output ddr3_cas_n,
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output ddr3_ras_n,
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output ddr3_we_n,
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output ddr3_ck_n,
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output ddr3_ck_p,
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output ddr3_cke,
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output ddr3_cs_n,
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output [ 7:0] ddr3_dm,
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inout [63:0] ddr3_dq,
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inout [ 7:0] ddr3_dqs_n,
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inout [ 7:0] ddr3_dqs_p,
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output ddr3_odt,
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output mdio_mdc,
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inout mdio_mdio,
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output mii_rst_n,
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input mii_col,
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input mii_crs,
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input mii_rx_clk,
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input mii_rx_er,
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input mii_rx_dv,
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input [ 3:0] mii_rxd,
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input mii_tx_clk,
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output mii_tx_en,
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output [ 3:0] mii_txd,
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output [26:1] linear_flash_addr,
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output linear_flash_adv_ldn,
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output linear_flash_ce_n,
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inout [15:0] linear_flash_dq_io,
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output linear_flash_oen,
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output linear_flash_wen,
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output fan_pwm,
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inout [ 6:0] gpio_lcd,
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inout [16:0] gpio_bd,
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output iic_rstn,
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inout iic_scl,
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inout iic_sda,
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input rx_ref_clk_p,
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input rx_ref_clk_n,
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input rx_sysref_p,
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input rx_sysref_n,
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output rx_sync_p,
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output rx_sync_n,
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input [ 3:0] rx_data_p,
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input [ 3:0] rx_data_n,
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input tx_ref_clk_p,
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input tx_ref_clk_n,
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input tx_sysref_p,
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input tx_sysref_n,
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input tx_sync_p,
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input tx_sync_n,
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output [ 3:0] tx_data_p,
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output [ 3:0] tx_data_n,
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input trig_p,
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input trig_n,
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inout adc_fdb,
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inout adc_fda,
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inout dac_irq,
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inout [ 1:0] clkd_status,
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inout adc_pd,
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inout dac_txen,
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inout dac_reset,
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inout clkd_sync,
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output spi_csn_clk,
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output spi_csn_dac,
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output spi_csn_adc,
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output spi_clk,
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inout spi_sdio,
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output spi_dir);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 7:0] spi_csn;
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wire spi_mosi;
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wire spi_miso;
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wire trig;
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wire rx_ref_clk;
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wire rx_sysref;
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wire rx_sync;
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wire tx_ref_clk;
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wire tx_sysref;
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wire tx_sync;
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// spi
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assign spi_csn_adc = spi_csn[2];
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assign spi_csn_dac = spi_csn[1];
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assign spi_csn_clk = spi_csn[0];
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// default logic
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assign ddr3_1_p = 2'b11;
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assign ddr3_1_n = 3'b000;
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assign fan_pwm = 1'b1;
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assign iic_rstn = 1'b1;
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// instantiations
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IBUFDS_GTE2 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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.I (rx_ref_clk_p),
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.IB (rx_ref_clk_n),
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.O (rx_ref_clk),
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.ODIV2 ());
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IBUFDS i_ibufds_rx_sysref (
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.I (rx_sysref_p),
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.IB (rx_sysref_n),
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.O (rx_sysref));
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OBUFDS i_obufds_rx_sync (
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.I (rx_sync),
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.O (rx_sync_p),
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.OB (rx_sync_n));
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IBUFDS_GTE2 i_ibufds_tx_ref_clk (
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.CEB (1'd0),
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.I (tx_ref_clk_p),
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.IB (tx_ref_clk_n),
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.O (tx_ref_clk),
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.ODIV2 ());
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IBUFDS i_ibufds_tx_sysref (
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.I (tx_sysref_p),
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.IB (tx_sysref_n),
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.O (tx_sysref));
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IBUFDS i_ibufds_tx_sync (
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.I (tx_sync_p),
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.IB (tx_sync_n),
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.O (tx_sync));
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daq2_spi i_spi (
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.spi_csn (spi_csn[2:0]),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio),
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.spi_dir (spi_dir));
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IBUFDS i_ibufds_trig (
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.I (trig_p),
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.IB (trig_n),
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.O (trig));
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assign gpio_i[43] = trig;
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ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
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.dio_t ({gpio_t[42:40], gpio_t[38], gpio_t[36:32]}),
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.dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
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.dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
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.dio_p ({ adc_pd, // 42
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dac_txen, // 41
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dac_reset, // 40
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clkd_sync, // 38
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adc_fdb, // 36
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adc_fda, // 35
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dac_irq, // 34
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clkd_status})); // 33-32
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ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
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.dio_t (gpio_t[16:0]),
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.dio_i (gpio_o[16:0]),
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.dio_o (gpio_i[16:0]),
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.dio_p (gpio_bd));
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assign gpio_i[63:44] = gpio_o[63:44];
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assign gpio_i[39] = gpio_o[39];
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assign gpio_i[37] = gpio_o[37];
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assign gpio_i[31:17] = gpio_o[31:17];
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system_wrapper i_system_wrapper (
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_cs_n (ddr3_cs_n),
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.ddr3_dm (ddr3_dm),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.ddr3_odt (ddr3_odt),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.gpio0_i (gpio_i[31:0]),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio1_i (gpio_i[63:32]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.gpio_lcd_tri_io (gpio_lcd),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.linear_flash_addr (linear_flash_addr),
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.linear_flash_adv_ldn (linear_flash_adv_ldn),
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.linear_flash_ce_n (linear_flash_ce_n),
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.linear_flash_dq_io (linear_flash_dq_io),
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.linear_flash_oen (linear_flash_oen),
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.linear_flash_wen (linear_flash_wen),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.mii_col (mii_col),
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.mii_crs (mii_crs),
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.mii_rst_n (mii_rst_n),
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.mii_rx_clk (mii_rx_clk),
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.mii_rx_dv (mii_rx_dv),
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.mii_rx_er (mii_rx_er),
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.mii_rxd (mii_rxd),
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.mii_tx_clk (mii_tx_clk),
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.mii_tx_en (mii_tx_en),
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.mii_txd (mii_txd),
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.rx_data_0_n (rx_data_n[0]),
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.rx_data_0_p (rx_data_p[0]),
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.rx_data_1_n (rx_data_n[1]),
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.rx_data_1_p (rx_data_p[1]),
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.rx_data_2_n (rx_data_n[2]),
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.rx_data_2_p (rx_data_p[2]),
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.rx_data_3_n (rx_data_n[3]),
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.rx_data_3_p (rx_data_p[3]),
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.rx_ref_clk_0 (rx_ref_clk),
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.rx_sync_0 (rx_sync),
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.rx_sysref_0 (rx_sysref),
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.spi_clk_i (spi_clk),
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.spi_clk_o (spi_clk),
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.spi_csn_i (spi_csn),
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.spi_csn_o (spi_csn),
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.spi_sdi_i (spi_miso),
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.spi_sdo_i (spi_mosi),
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.spi_sdo_o (spi_mosi),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.tx_data_0_n (tx_data_n[0]),
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.tx_data_0_p (tx_data_p[0]),
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.tx_data_1_n (tx_data_n[1]),
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.tx_data_1_p (tx_data_p[1]),
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.tx_data_2_n (tx_data_n[2]),
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.tx_data_2_p (tx_data_p[2]),
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.tx_data_3_n (tx_data_n[3]),
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.tx_data_3_p (tx_data_p[3]),
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.tx_ref_clk_0 (tx_ref_clk),
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.tx_sync_0 (tx_sync),
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.tx_sysref_0 (tx_sysref),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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