98 lines
3.3 KiB
Verilog
98 lines
3.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// Color Space Conversion, multiplier. This is a simple partial product adder
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// that generates the product of the two inputs.
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`timescale 1ps/1ps
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module ad_csc_1_mul #(
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parameter DELAY_DATA_WIDTH = 16) (
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// data_a is signed
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input clk,
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input [16:0] data_a,
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input [ 7:0] data_b,
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output [24:0] data_p,
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// delay match
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input [(DELAY_DATA_WIDTH-1):0] ddata_in,
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output [(DELAY_DATA_WIDTH-1):0] ddata_out);
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// internal registers
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reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
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reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
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reg [(DELAY_DATA_WIDTH-1):0] p3_ddata = 'd0;
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reg p1_sign = 'd0;
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reg p2_sign = 'd0;
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reg p3_sign = 'd0;
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// internal signals
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wire [33:0] p3_data_s;
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// a/b reg, m-reg, p-reg delay match
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always @(posedge clk) begin
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p1_ddata <= ddata_in;
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p2_ddata <= p1_ddata;
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p3_ddata <= p2_ddata;
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end
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always @(posedge clk) begin
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p1_sign <= data_a[16];
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p2_sign <= p1_sign;
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p3_sign <= p2_sign;
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end
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assign ddata_out = p3_ddata;
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assign data_p = {p3_sign, p3_data_s[23:0]};
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ad_mul ad_mul_1 (
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.clk(clk),
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.data_a({1'b0, data_a[15:0]}),
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.data_b({9'b0, data_b}),
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.data_p(p3_data_s),
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.ddata_in(16'h0),
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.ddata_out());
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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