Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl		2019-06-29 06:53:51 +03:00
..
Makefile	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
axi_ad9152.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
axi_ad9152_constr.xdc	axi_ad9152: Added CDC and reset constraints	2015-04-23 10:21:52 +03:00
axi_ad9152_hw.tcl	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
axi_ad9152_ip.tcl	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00