Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl		2019-06-29 06:53:51 +03:00
..
Makefile	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
axi_ad9684.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
axi_ad9684_channel.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
axi_ad9684_constr.sdc	ad9684- fix sdc typo	2017-03-23 12:49:44 -04:00
axi_ad9684_constr.xdc	axi_ad9684: Fix constraint file	2016-02-12 14:38:59 +02:00
axi_ad9684_hw.tcl	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
axi_ad9684_if.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
axi_ad9684_ip.tcl	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00
axi_ad9684_pnmon.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00