Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl		2019-06-29 06:53:51 +03:00
..
Makefile	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
ad_ip_jesd204_tpl_adc.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
ad_ip_jesd204_tpl_adc_channel.v	ad_ip_jesd204_tpl_adc: Add 8 bit resolution support	2019-03-20 15:51:28 +02:00
ad_ip_jesd204_tpl_adc_core.v	ad_ip_jesd204_tpl_adc: Add 8 bit resolution support	2019-03-20 15:51:28 +02:00
ad_ip_jesd204_tpl_adc_deframer.v	ad_ip_jesd204_tpl_adc: make core more generic	2018-12-04 14:02:22 +02:00
ad_ip_jesd204_tpl_adc_hw.tcl	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
ad_ip_jesd204_tpl_adc_ip.tcl	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00
ad_ip_jesd204_tpl_adc_pnmon.v	ad_ip_jesd204_tpl_adc: make core more generic	2018-12-04 14:02:22 +02:00
ad_ip_jesd204_tpl_adc_regmap.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00