36422f0454
We can remove the Altera toplevel wrapper if we switch the axi4 control bus to axi4lite and add the few missing signals that are required by the Altera interconnect to both the control and the data buses. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
hdl
Analog Devices HDL libraries and projects
First time users, it is highly recommended to go through our HDL user guide at the following url:
http://wiki.analog.com/resources/fpga/docs/hdl
For support please visit our FPGA Reference Designs Support Community on EngineerZone: