53 lines
3.2 KiB
Plaintext
53 lines
3.2 KiB
Plaintext
set_property ASYNC_REG TRUE \
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[get_cells -hier *dma_mem_*_m*] \
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[get_cells -hier *axi_xfer_*_m*] \
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[get_cells -hier *axi_mem_*_m*] \
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[get_cells -hier *axi_dma_*_m*] \
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[get_cells -hier *dac_mem_*_m*] \
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[get_cells -hier *dac_xfer_*_m*] \
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[get_cells -hier *dac_last_*_m*] \
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[get_cells -hier *dac_bypass_m*]
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# AXI clk to DMA clk
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set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_raddr_g* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ */dma_mem_raddr_m1* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_last_read_toggle* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ */dma_mem_last_read_toggle_m_* && IS_SEQUENTIAL}]
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# DAC clk to DMA clk
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set_false_path -from [get_cells -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ */dma_mem_raddr_m1_* && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ */dma_rst_m1_reg && IS_SEQUENTIAL}]
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# DMA clk to AXI clk
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set_false_path -from [get_cells -hier -filter {name =~ */dma_last_beats* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ */axi_dma_last_beats_m1* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ */axi_mem_waddr_m1* && IS_SEQUENTIAL}]
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#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
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set_false_path -through [get_pins -hier -filter {name =~ */axi_xfer_req_m_reg[0]/D}]
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# DAC clk to AXI clk
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set_false_path -from [get_cells -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ */axi_mem_raddr_m1* && IS_SEQUENTIAL}]
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# DMA clk to DAC clk
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set_false_path -from [get_cells -hier -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ */dma_last_beats* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ */dac_last_beats_m* && IS_SEQUENTIAL}]
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#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
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set_false_path -through [get_pins -hier -filter {name =~ */dac_xfer_out_m1_reg*/D}]
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# AXI clk to DAC clk
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set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_laddr* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ */dac_mem_laddr* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_laddr_toggle* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ */dac_mem_laddr_toggle_m* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_waddr_g* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}]
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#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
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set_false_path -through [get_pins -hier -filter {name =~ */dac_xfer_req_m_reg[0]/D}]
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