110 lines
3.1 KiB
Tcl
110 lines
3.1 KiB
Tcl
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set xl_board "none"
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proc adi_project_create {project_name} {
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global ad_hdl_dir
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global ad_phdl_dir
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global xl_board
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set xl_board "none"
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set project_part "none"
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set project_board "none"
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if [regexp "_ac701$" $project_name] {
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set xl_board "ac701"
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set project_part "xc7a200tfbg676-2"
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set project_board "xilinx.com:artix7:ac701:1.0"
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}
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if [regexp "_kc705$" $project_name] {
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set xl_board "kc705"
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set project_part "xc7k325tffg900-2"
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set project_board "xilinx.com:kintex7:kc705:1.1"
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}
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if [regexp "_vc707$" $project_name] {
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set xl_board "vc707"
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set project_part "xc7vx485tffg1761-2"
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set project_board "xilinx.com:virtex7:vc707:1.1"
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}
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if [regexp "_zed$" $project_name] {
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set xl_board "zed"
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set project_part "xc7z020clg484-1"
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set project_board "em.avnet.com:zynq:zed:d"
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}
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if [regexp "_zc702$" $project_name] {
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set xl_board "zc702"
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set project_part "xc7z020clg484-1"
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set project_board "xilinx.com:zynq:zc702:1.0"
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}
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if [regexp "_zc706$" $project_name] {
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set xl_board "zc706"
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set project_part "xc7z045ffg900-2"
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set project_board "xilinx.com:zynq:zc706:1.1"
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}
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set project_system_dir "./$project_name.srcs/sources_1/bd/system"
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create_project $project_name . -part $project_part -force
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set_property board $project_board [current_project]
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set lib_dirs $ad_hdl_dir/library
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if {$ad_hdl_dir ne $ad_phdl_dir} {
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lappend lib_dirs $ad_phdl_dir/library
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}
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set_property ip_repo_paths $lib_dirs [current_fileset]
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update_ip_catalog
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create_bd_design "system"
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source system_bd.tcl
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generate_target {synthesis implementation} [get_files $project_system_dir/system.bd]
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make_wrapper -files [get_files $project_system_dir/system.bd] -top
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import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v
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}
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proc adi_project_files {project_name project_files} {
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global ad_hdl_dir
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global ad_phdl_dir
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add_files -norecurse -fileset sources_1 $project_files
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set_property top system_top [current_fileset]
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}
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proc adi_project_run {project_name} {
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global ad_hdl_dir
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global ad_phdl_dir
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set project_system_dir "./$project_name.srcs/sources_1/bd/system"
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set_property constrs_type XDC [current_fileset -constrset]
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launch_runs synth_1
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wait_on_run synth_1
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open_run synth_1
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report_timing_summary -file timing_synth.log
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set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
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set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
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set_property STRATEGY "Performance_Explore" [get_runs impl_1]
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launch_runs impl_1 -to_step write_bitstream
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wait_on_run impl_1
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open_run impl_1
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report_timing_summary -file timing_impl.log
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#get_property STATS.THS [get_runs impl_1]
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#get_property STATS.TNS [get_runs impl_1]
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#get_property STATS.TPWS [get_runs impl_1]
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if [expr [get_property SLACK [get_timing_paths]] < 0] {
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puts "ERROR: Timing Constraints NOT met."
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use_this_invalid_command_to_crash
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}
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export_hardware [get_files $project_system_dir/system.bd] [get_runs impl_1] -bitstream
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}
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