102 lines
3.1 KiB
Verilog
102 lines
3.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_dds #(
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// data path disable
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parameter DISABLE = 0) (
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// interface
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input clk,
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input dds_format,
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input [15:0] dds_phase_0,
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input [15:0] dds_scale_0,
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input [15:0] dds_phase_1,
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input [15:0] dds_scale_1,
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output [15:0] dds_data);
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// internal registers
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reg [15:0] dds_data_int = 'd0;
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reg [15:0] dds_data_out = 'd0;
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reg [15:0] dds_scale_0_d = 'd0;
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reg [15:0] dds_scale_1_d = 'd0;
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// internal signals
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wire [15:0] dds_data_0_s;
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wire [15:0] dds_data_1_s;
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// disable
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assign dds_data = (DISABLE == 1) ? 16'd0 : dds_data_out;
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// dds channel output
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always @(posedge clk) begin
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dds_data_int <= dds_data_0_s + dds_data_1_s;
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dds_data_out[15:15] <= dds_data_int[15] ^ dds_format;
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dds_data_out[14: 0] <= dds_data_int[14:0];
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end
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always @(posedge clk) begin
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dds_scale_0_d <= dds_scale_0;
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dds_scale_1_d <= dds_scale_1;
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end
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// dds-1
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ad_dds_1 i_dds_1_0 (
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.clk (clk),
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.angle (dds_phase_0),
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.scale (dds_scale_0_d),
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.dds_data (dds_data_0_s));
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// dds-2
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ad_dds_1 i_dds_1_1 (
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.clk (clk),
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.angle (dds_phase_1),
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.scale (dds_scale_1_d),
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.dds_data (dds_data_1_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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