218 lines
6.7 KiB
Verilog
218 lines
6.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad7616_control #(
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parameter ID = 0,
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parameter IF_TYPE = 0) (
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// control signals
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output cnvst,
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input busy,
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input [15:0] up_read_data,
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input up_read_valid,
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output reg [15:0] up_write_data,
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output up_read_req,
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output up_write_req,
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output reg [ 4:0] up_burst_length,
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output end_of_conv,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack
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);
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localparam PCORE_VERSION = 'h0001001;
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localparam POS_EDGE = 0;
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localparam NEG_EDGE = 1;
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localparam SERIAL = 0;
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localparam PARALLEL = 1;
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// internal signals
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reg [31:0] up_scratch = 32'b0;
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reg up_resetn = 1'b0;
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reg up_cnvst_en = 1'b0;
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reg [31:0] up_conv_rate = 32'b0;
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reg [31:0] cnvst_counter = 32'b0;
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reg [ 3:0] pulse_counter = 8'b0;
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reg cnvst_buf = 1'b0;
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reg cnvst_pulse = 1'b0;
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reg [ 2:0] chsel_ff = 3'b0;
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wire up_rst;
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wire up_rreq_s;
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wire up_rack_s;
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wire up_wreq_s;
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wire [31:0] up_read_data_s;
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wire up_read_valid_s;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == 6'h01) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == 6'h01) ? up_rreq : 1'b0;
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// the up_[read/write]_data interfaces are valid just in parallel mode
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assign up_read_valid_s = (IF_TYPE == PARALLEL) ? up_read_valid : 1'b1;
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assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : {2{16'hDEAD}};
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 1'h0;
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up_scratch <= 32'b0;
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up_resetn <= 1'b0;
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up_cnvst_en <= 1'b0;
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up_conv_rate <= 32'b0;
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up_burst_length <= 5'h0;
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up_write_data <= 16'h0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
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up_resetn <= up_wdata[0];
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up_cnvst_en <= up_wdata[1];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
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up_conv_rate <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
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up_burst_length <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
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up_write_data <= up_wdata;
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end
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end
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end
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assign up_write_req = (up_waddr[7:0] == 8'h14) ? up_wreq_s : 1'h0;
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// processor read interface
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assign up_rack_s = (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s;
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assign up_read_req = (up_raddr[7:0] == 8'h13) ? up_rreq_s : 1'b0;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 1'b0;
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up_rdata <= 32'b0;
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end else begin
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up_rack <= up_rack_s;
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if (up_rack_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h00 : up_rdata = PCORE_VERSION;
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8'h01 : up_rdata = ID;
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8'h02 : up_rdata = up_scratch;
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8'h03 : up_rdata = IF_TYPE;
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8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
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8'h11 : up_rdata = up_conv_rate;
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8'h12 : up_rdata = {27'b0, up_burst_length};
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8'h13 : up_rdata = up_read_data_s;
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endcase
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end
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end
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end
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// instantiations
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assign up_rst = ~up_rstn;
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ad_edge_detect #(
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.EDGE(NEG_EDGE)
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) i_ad_edge_detect (
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.clk (up_clk),
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.rst (up_rst),
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.in (busy),
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.out (end_of_conv)
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);
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// convertion start generator
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// NOTE: + The minimum convertion cycle is 1 us
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// + The rate of the cnvst must be defined in a way,
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// to not lose any data. cnvst_rate >= t_conversion + t_aquisition
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// See the AD7616 datasheet for more information.
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always @(posedge up_clk) begin
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if(up_resetn == 1'b0) begin
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cnvst_counter <= 32'b0;
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end else begin
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cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0;
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end
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end
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always @(cnvst_counter, up_conv_rate) begin
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cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0;
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end
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always @(posedge up_clk) begin
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if(up_resetn == 1'b0) begin
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pulse_counter <= 3'b0;
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cnvst_buf <= 1'b0;
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end else begin
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pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 3'b0;
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if(cnvst_pulse == 1'b1) begin
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cnvst_buf <= 1'b1;
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end else if (pulse_counter[2] == 1'b1) begin
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cnvst_buf <= 1'b0;
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end
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end
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end
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assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
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endmodule
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