485 lines
16 KiB
Verilog
485 lines
16 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adc_trigger(
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input clk,
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input [ 1:0] trigger_i,
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output [ 1:0] trigger_o,
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output [ 1:0] trigger_t,
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input [15:0] data_a,
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input [15:0] data_b,
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input data_valid_a,
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input data_valid_b,
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output [15:0] data_a_trig,
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output [15:0] data_b_trig,
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output data_valid_a_trig,
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output data_valid_b_trig,
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output [31:0] fifo_depth,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 6:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 6:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire [ 4:0] up_waddr;
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wire [31:0] up_wdata;
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wire up_wack;
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wire up_wreq;
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wire up_rack;
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wire [31:0] up_rdata;
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wire up_rreq;
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wire [ 4:0] up_raddr;
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wire [ 1:0] io_selection;
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wire [ 1:0] low_level;
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wire [ 1:0] high_level;
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wire [ 1:0] any_edge;
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wire [ 1:0] rise_edge;
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wire [ 1:0] fall_edge;
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wire [15:0] limit_a;
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wire [ 1:0] function_a;
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wire [31:0] hysteresis_a;
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wire [ 3:0] trigger_l_mix_a;
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wire [15:0] limit_b;
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wire [ 1:0] function_b;
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wire [31:0] hysteresis_b;
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wire [ 3:0] trigger_l_mix_b;
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wire [ 2:0] trigger_out_mix;
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wire [31:0] trigger_delay;
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wire [15:0] data_a_cmp;
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wire [15:0] data_b_cmp;
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wire [15:0] limit_a_cmp;
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wire [15:0] limit_b_cmp;
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wire trigger_a_fall_edge;
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wire trigger_a_rise_edge;
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wire trigger_b_fall_edge;
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wire trigger_b_rise_edge;
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wire trigger_a_any_edge;
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wire trigger_b_any_edge;
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wire trigger_out_a;
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wire trigger_out_b;
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wire trigger_out_delayed;
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wire streaming;
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reg trigger_a_d1; // synchronization flip flop
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reg trigger_a_d2; // synchronization flip flop
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reg trigger_a_d3;
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reg trigger_b_d1; // synchronization flip flop
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reg trigger_b_d2; // synchronization flip flop
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reg trigger_b_d3;
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reg passthrough_high_a; // trigger when rising through the limit
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reg passthrough_low_a; // trigger when fallingh thorugh the limit
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reg low_a; // signal was under the limit, so if it goes through, assert rising
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reg high_a; // signal was over the limit, so if it passes through, assert falling
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reg comp_high_a; // signal is over the limit
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reg comp_low_a; // signal is under the limit
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reg passthrough_high_b; // trigger when rising through the limit
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reg passthrough_low_b; // trigger when fallingh thorugh the limit
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reg low_b; // signal was under the limit, so if it goes through, assert rising
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reg high_b; // signal was over the limit, so if it passes through, assert falling
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reg comp_high_b; // signal is over the limit
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reg comp_low_b; // signal is under the limit
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reg trigger_pin_a;
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reg trigger_pin_b;
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reg trigger_adc_a;
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reg trigger_adc_b;
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reg trigger_a;
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reg trigger_b;
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reg trigger_out_mixed;
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reg up_triggered;
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reg up_triggered_d1;
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reg up_triggered_d2;
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reg up_triggered_set;
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reg up_triggered_reset;
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reg up_triggered_reset_d1;
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reg up_triggered_reset_d2;
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reg [14:0] data_a_r;
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reg [14:0] data_b_r;
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reg data_valid_a_r;
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reg data_valid_b_r;
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reg [31:0] trigger_delay_counter;
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reg triggered;
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reg streaming_on;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign trigger_t = io_selection;
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assign trigger_a_fall_edge = (trigger_a_d2 == 1'b0 && trigger_a_d3 == 1'b1) ? 1'b1: 1'b0;
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assign trigger_a_rise_edge = (trigger_a_d2 == 1'b1 && trigger_a_d3 == 1'b0) ? 1'b1: 1'b0;
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assign trigger_a_any_edge = trigger_a_rise_edge | trigger_a_fall_edge;
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assign trigger_b_fall_edge = (trigger_b_d2 == 1'b0 && trigger_b_d3 == 1'b1) ? 1'b1: 1'b0;
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assign trigger_b_rise_edge = (trigger_b_d2 == 1'b1 && trigger_b_d3 == 1'b0) ? 1'b1: 1'b0;
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assign trigger_b_any_edge = trigger_b_rise_edge | trigger_b_fall_edge;
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assign data_a_cmp = {!data_a[15],data_a[14:0]};
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assign data_b_cmp = {!data_b[15],data_b[14:0]};
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assign limit_a_cmp = {!limit_a[15],limit_a[14:0]};
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assign limit_b_cmp = {!limit_b[15],limit_b[14:0]};
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assign data_a_trig = trigger_delay == 32'h0 ? {trigger_out_mixed | streaming_on, data_a_r} : {trigger_out_delayed |streaming_on, data_a_r};
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assign data_b_trig = trigger_delay == 32'h0 ? {trigger_out_mixed | streaming_on, data_b_r} : {trigger_out_delayed |streaming_on, data_b_r};
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assign data_valid_a_trig = data_valid_a_r;
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assign data_valid_b_trig = data_valid_b_r;
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assign trigger_out_delayed = (trigger_delay_counter == 32'h0) ? 1 : 0;
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always @(posedge clk) begin
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if (trigger_delay == 0) begin
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trigger_delay_counter <= 32'h0;
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end else begin
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if (data_valid_a_r == 1'b1) begin
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triggered <= trigger_out_mixed | triggered;
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if (trigger_delay_counter == 0) begin
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trigger_delay_counter <= trigger_delay;
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triggered <= 1'b0;
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end else begin
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if(triggered == 1'b1 || trigger_out_mixed == 1'b1) begin
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trigger_delay_counter <= trigger_delay_counter - 1;
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end
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end
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end
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end
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end
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always @(posedge clk) begin
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if (trigger_delay == 0) begin
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if (streaming == 1'b1 && data_valid_a_r == 1'b1 && trigger_out_mixed == 1'b1) begin
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streaming_on <= 1'b1;
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end else if (streaming == 1'b0) begin
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streaming_on <= 1'b0;
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end
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end else begin
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if (streaming == 1'b1 && data_valid_a_r == 1'b1 && trigger_out_delayed == 1'b1) begin
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streaming_on <= 1'b1;
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end else if (streaming == 1'b0) begin
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streaming_on <= 1'b0;
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end
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end
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end
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always @(posedge clk) begin
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if (data_valid_a_r == 1'b1 && trigger_out_mixed == 1'b1) begin
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up_triggered_set <= 1'b1;
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end else if (up_triggered_reset == 1'b1) begin
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up_triggered_set <= 1'b0;
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end
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up_triggered_reset_d1 <= up_triggered;
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up_triggered_reset_d2 <= up_triggered_reset_d1;
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up_triggered_reset <= up_triggered_reset_d2;
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end
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always @(posedge up_clk) begin
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up_triggered_d1 <= up_triggered_set;
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up_triggered_d2 <= up_triggered_d1;
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up_triggered <= up_triggered_d2;
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end
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always @(posedge clk) begin
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data_a_r <= data_a[14:0];
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data_valid_a_r <= data_valid_a;
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data_b_r <= data_b[14:0];
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data_valid_b_r <= data_valid_b;
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end
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always @(*) begin
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case(trigger_l_mix_a)
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4'h0: trigger_a = 1'b1;
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4'h1: trigger_a = trigger_pin_a;
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4'h2: trigger_a = trigger_adc_a;
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4'h4: trigger_a = trigger_pin_a | trigger_adc_a ;
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4'h5: trigger_a = trigger_pin_a & trigger_adc_a ;
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4'h6: trigger_a = trigger_pin_a ^ trigger_adc_a ;
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4'h7: trigger_a = !(trigger_pin_a | trigger_adc_a) ;
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4'h8: trigger_a = !(trigger_pin_a & trigger_adc_a) ;
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4'h9: trigger_a = !(trigger_pin_a ^ trigger_adc_a) ;
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default: trigger_a = 1'b1;
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endcase
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end
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always @(*) begin
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case(trigger_l_mix_b)
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4'h0: trigger_b = 1'b1;
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4'h1: trigger_b = trigger_pin_b;
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4'h2: trigger_b = trigger_adc_b;
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4'h4: trigger_b = trigger_pin_b | trigger_adc_b ;
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4'h5: trigger_b = trigger_pin_b & trigger_adc_b ;
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4'h6: trigger_b = trigger_pin_b ^ trigger_adc_b ;
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4'h7: trigger_b = !(trigger_pin_b | trigger_adc_b) ;
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4'h8: trigger_b = !(trigger_pin_b & trigger_adc_b) ;
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4'h9: trigger_b = !(trigger_pin_b ^ trigger_adc_b) ;
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default: trigger_b = 1'b1;
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endcase
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end
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always @(*) begin
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case(function_a)
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2'h0: trigger_adc_a = comp_low_a;
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2'h1: trigger_adc_a = comp_high_a;
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2'h2: trigger_adc_a = passthrough_high_a;
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2'h3: trigger_adc_a = passthrough_low_a;
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default: trigger_adc_a = comp_low_a;
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endcase
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end
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always @(*) begin
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case(function_b)
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2'h0: trigger_adc_b = comp_low_b;
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2'h1: trigger_adc_b = comp_high_b;
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2'h2: trigger_adc_b = passthrough_high_b;
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2'h3: trigger_adc_b = passthrough_low_b;
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default: trigger_adc_b = comp_low_b;
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endcase
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end
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always @(posedge clk) begin
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trigger_a_d1 <= trigger_i[0];
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trigger_a_d2 <= trigger_a_d1;
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trigger_a_d3 <= trigger_a_d2;
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trigger_b_d1 <= trigger_i[1];
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trigger_b_d2 <= trigger_b_d1;
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trigger_b_d3 <= trigger_b_d2;
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end
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always @(*) begin
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trigger_pin_a = ((!trigger_a_d3 & low_level[0]) |
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(trigger_a_d3 & high_level[0]) |
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(trigger_a_fall_edge & fall_edge[0]) |
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(trigger_a_rise_edge & rise_edge[0]) |
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(trigger_a_any_edge & any_edge[0]));
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end
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always @(*) begin
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trigger_pin_b = ((!trigger_b_d3 & low_level[1]) |
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(trigger_b_d3 & high_level[1]) |
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(trigger_b_fall_edge & fall_edge[1]) |
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(trigger_b_rise_edge & rise_edge[1]) |
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(trigger_b_any_edge & any_edge[1]));
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end
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always @(*) begin
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case(trigger_out_mix)
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3'h0: trigger_out_mixed = trigger_a;
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3'h1: trigger_out_mixed = trigger_b;
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3'h2: trigger_out_mixed = trigger_a | trigger_b;
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3'h3: trigger_out_mixed = trigger_a & trigger_b;
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3'h4: trigger_out_mixed = trigger_a ^ trigger_b;
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default: trigger_out_mixed = trigger_a;
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endcase
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end
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always @(posedge clk) begin
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if (data_valid_a == 1'b1) begin
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if (data_a_cmp > limit_a_cmp) begin
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comp_high_a <= 1'b1;
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passthrough_high_a <= low_a;
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end else begin
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comp_high_a <= 1'b0;
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passthrough_high_a <= 1'b0;
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end
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if (data_a_cmp < limit_a_cmp) begin
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comp_low_a <= 1'b1;
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passthrough_low_a <= high_a;
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end else begin
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comp_low_a <= 1'b0;
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passthrough_low_a <= 1'b0;
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end
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if (passthrough_high_a == 1'b1) begin
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low_a <= 1'b0;
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end else if (data_a_cmp < limit_a_cmp - hysteresis_a) begin
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low_a <= 1'b1;
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end
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if (passthrough_low_a == 1'b1) begin
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high_a <= 1'b0;
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end else if (data_a_cmp > limit_a_cmp + hysteresis_a) begin
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high_a <= 1'b1;
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end
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end
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end
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always @(posedge clk) begin
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if (data_valid_b == 1'b1) begin
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if (data_b_cmp > limit_b_cmp) begin
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comp_high_b <= 1'b1;
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passthrough_high_b <= low_b;
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end else begin
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comp_high_b <= 1'b0;
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passthrough_high_b <= 1'b0;
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end
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if (data_b_cmp < limit_b_cmp) begin
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comp_low_b <= 1'b1;
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passthrough_low_b <= high_b;
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end else begin
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comp_low_b <= 1'b0;
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passthrough_low_b <= 1'b0;
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end
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if (trigger_b == 1'b1) begin
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low_b <= 1'b0;
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high_b <= 1'b0;
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end else if (data_b_cmp < limit_b_cmp - hysteresis_b) begin
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low_b <= 1'b1;
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end else if (data_b_cmp > limit_b_cmp + hysteresis_b) begin
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high_b <= 1'b1;
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end
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end
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end
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axi_adc_trigger_reg adc_trigger_registers (
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.clk(clk),
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.io_selection(io_selection),
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.trigger_o(trigger_o),
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.triggered(up_triggered),
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.low_level(low_level),
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.high_level(high_level),
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.any_edge(any_edge),
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.rise_edge(rise_edge),
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.fall_edge(fall_edge),
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.limit_a(limit_a),
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.function_a(function_a),
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.hysteresis_a(hysteresis_a),
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.trigger_l_mix_a(trigger_l_mix_a),
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.limit_b(limit_b),
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.function_b(function_b),
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.hysteresis_b(hysteresis_b),
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.trigger_l_mix_b(trigger_l_mix_b),
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.trigger_out_mix(trigger_out_mix),
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.trigger_delay(trigger_delay),
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.fifo_depth(fifo_depth),
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.streaming(streaming),
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// bus interface
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_wack(up_wack),
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.up_rreq(up_rreq),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata),
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.up_rack(up_rack));
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up_axi #(
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.AXI_ADDRESS_WIDTH(7),
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.ADDRESS_WIDTH(5)
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) i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
|
|
.up_axi_wdata (s_axi_wdata),
|
|
.up_axi_wstrb (s_axi_wstrb),
|
|
.up_axi_wready (s_axi_wready),
|
|
.up_axi_bvalid (s_axi_bvalid),
|
|
.up_axi_bresp (s_axi_bresp),
|
|
.up_axi_bready (s_axi_bready),
|
|
.up_axi_arvalid (s_axi_arvalid),
|
|
.up_axi_araddr (s_axi_araddr),
|
|
.up_axi_arready (s_axi_arready),
|
|
.up_axi_rvalid (s_axi_rvalid),
|
|
.up_axi_rresp (s_axi_rresp),
|
|
.up_axi_rdata (s_axi_rdata),
|
|
.up_axi_rready (s_axi_rready),
|
|
.up_wreq (up_wreq),
|
|
.up_waddr (up_waddr),
|
|
.up_wdata (up_wdata),
|
|
.up_wack (up_wack),
|
|
.up_rreq (up_rreq),
|
|
.up_raddr (up_raddr),
|
|
.up_rdata (up_rdata),
|
|
.up_rack (up_rack));
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|
|
|
endmodule
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|
|
|
// ***************************************************************************
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// ***************************************************************************
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