108 lines
3.2 KiB
Verilog
108 lines
3.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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module fifo_address_sync #(
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parameter ADDRESS_WIDTH = 4
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) (
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input clk,
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input resetn,
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input m_axis_ready,
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output reg m_axis_valid,
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output reg [ADDRESS_WIDTH-1:0] m_axis_raddr,
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output [ADDRESS_WIDTH:0] m_axis_level,
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output reg s_axis_ready,
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input s_axis_valid,
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output reg s_axis_empty,
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output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
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output [ADDRESS_WIDTH:0] s_axis_room
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);
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localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
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reg [ADDRESS_WIDTH:0] room = MAX_ROOM;
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reg [ADDRESS_WIDTH:0] level = 'h00;
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reg [ADDRESS_WIDTH:0] level_next;
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assign s_axis_room = room;
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assign m_axis_level = level;
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wire read = m_axis_ready & m_axis_valid;
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wire write = s_axis_ready & s_axis_valid;
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always @(posedge clk)
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begin
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if (resetn == 1'b0) begin
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s_axis_waddr <= 'h00;
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m_axis_raddr <= 'h00;
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end else begin
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if (write)
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s_axis_waddr <= s_axis_waddr + 1'b1;
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if (read)
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m_axis_raddr <= m_axis_raddr + 1'b1;
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end
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end
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always @(*)
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begin
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if (read & ~write)
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level_next <= level - 1'b1;
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else if (~read & write)
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level_next <= level + 1'b1;
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else
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level_next <= level;
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end
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always @(posedge clk)
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begin
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if (resetn == 1'b0) begin
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m_axis_valid <= 1'b0;
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s_axis_ready <= 1'b0;
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level <= 'h00;
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room <= MAX_ROOM;
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s_axis_empty <= 'h00;
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end else begin
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level <= level_next;
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room <= MAX_ROOM - level_next;
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m_axis_valid <= level_next != 0;
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s_axis_ready <= level_next != MAX_ROOM;
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s_axis_empty <= level_next == 0;
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end
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end
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endmodule
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