af5c71a9b2
The Xilinx's reset interface expect that every reset have an associated interface and clock signal. The tool will try to find its clock and interface, and automatically associated clock signal to it. The PLL resets are individual asynchronous resets. To simplify the design and avoid invalid critical warnings all the reset interface inference for the PLL resets were removed. |
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| .. | ||
| Makefile | ||
| axi_adxcvr.v | ||
| axi_adxcvr_es.v | ||
| axi_adxcvr_ip.tcl | ||
| axi_adxcvr_mdrp.v | ||
| axi_adxcvr_mstatus.v | ||
| axi_adxcvr_up.v | ||