211 lines
6.5 KiB
Verilog
211 lines
6.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad7616 #(
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parameter ID = 0
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) (
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// physical data interface
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output rx_cs_n,
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output [15:0] rx_db_o,
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input [15:0] rx_db_i,
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output rx_db_t,
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output rx_rd_n,
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output rx_wr_n,
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// physical control interface
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input rx_trigger,
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// AXI Slave Memory Map
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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// Write FIFO interface
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output adc_valid,
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output [15:0] adc_data,
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output adc_sync
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);
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// internal registers
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reg up_wack = 1'b0;
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reg up_rack = 1'b0;
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reg [31:0] up_rdata = 32'b0;
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire up_rst;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_cntrl_s;
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wire up_rack_cntrl_s;
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wire [31:0] up_rdata_cntrl_s;
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wire trigger_s;
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wire rd_req_s;
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wire wr_req_s;
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wire [15:0] wr_data_s;
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wire [15:0] rd_data_s;
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wire rd_valid_s;
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wire [ 4:0] burst_length_s;
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// defaults
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign up_rst = ~s_axi_aresetn;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_wack <= up_wack_cntrl_s;
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up_rack <= up_rack_cntrl_s;
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up_rdata <= up_rdata_cntrl_s;
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end
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end
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axi_ad7616_pif i_ad7616_parallel_interface (
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.cs_n (rx_cs_n),
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.db_o (rx_db_o),
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.db_i (rx_db_i),
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.db_t (rx_db_t),
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.rd_n (rx_rd_n),
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.wr_n (rx_wr_n),
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.adc_data (adc_data),
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.adc_valid (adc_valid),
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.adc_sync (adc_sync),
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.end_of_conv (rx_trigger),
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.burst_length(burst_length_s),
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.clk (up_clk),
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.rstn (up_rstn),
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.rd_req (rd_req_s),
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.wr_req (wr_req_s),
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.wr_data (wr_data_s),
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.rd_data (rd_data_s),
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.rd_valid (rd_valid_s));
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axi_ad7616_control #(
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.ID(ID)
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) i_ad7616_control (
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.up_burst_length (burst_length_s),
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.up_read_data (rd_data_s),
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.up_read_valid (rd_valid_s),
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.up_write_data (wr_data_s),
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.up_read_req (rd_req_s),
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.up_write_req (wr_req_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_cntrl_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_cntrl_s),
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.up_rack (up_rack_cntrl_s));
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// up bus interface
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up_axi #(
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.AXI_ADDRESS_WIDTH (16)
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) i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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