179 lines
5.6 KiB
Verilog
179 lines
5.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9122_channel #(
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parameter CHANNEL_ID = 32'h0,
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parameter DAC_DDS_TYPE = 1,
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parameter DAC_DDS_CORDIC_DW = 16,
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parameter DAC_DDS_CORDIC_PHASE_DW = 16,
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parameter DATAPATH_DISABLE = 0
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) (
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// dac interface
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input dac_div_clk,
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input dac_rst,
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output reg dac_enable,
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output reg [63:0] dac_data,
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output reg [ 3:0] dac_frame,
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input [63:0] dma_data,
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// processor interface
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input dac_data_frame,
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input dac_data_sync,
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input dac_dds_format,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack
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);
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// internal signals
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wire [15:0] dac_dds_data_s;
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wire [15:0] dac_dds_scale_1_s;
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wire [15:0] dac_dds_init_1_s;
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wire [15:0] dac_dds_incr_1_s;
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wire [15:0] dac_dds_scale_2_s;
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wire [15:0] dac_dds_init_2_s;
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wire [15:0] dac_dds_incr_2_s;
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wire [15:0] dac_pat_data_1_s;
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wire [15:0] dac_pat_data_2_s;
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wire [ 3:0] dac_data_sel_s;
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// dac data select
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always @(posedge dac_div_clk) begin
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dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
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case (dac_data_sel_s)
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4'h2: dac_data <= dma_data;
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4'ha, 4'h1: dac_data <= {dac_pat_data_2_s, dac_pat_data_1_s,
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dac_pat_data_2_s, dac_pat_data_1_s};
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default: dac_data <= dac_dds_data_s;
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endcase
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if (dac_data_sel_s == 4'h1) begin
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dac_frame <= 4'b0101;
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end else begin
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dac_frame <= {3'd0, dac_data_frame};
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end
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end
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// dds
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ad_dds #(
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.DISABLE (DATAPATH_DISABLE),
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.DDS_DW (16),
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.PHASE_DW (16),
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.DDS_TYPE (DAC_DDS_TYPE),
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.CORDIC_DW (DAC_DDS_CORDIC_DW),
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.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
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.CLK_RATIO (4)
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) i_dds (
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.clk (dac_clk),
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.dac_dds_format (dac_dds_format),
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.dac_data_sync (dac_data_sync),
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.dac_valid (1'b1),
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.tone_1_scale (dac_dds_scale_1_s),
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.tone_2_scale (dac_dds_scale_2_s),
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.tone_1_init_offset (dac_dds_init_1_s),
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.tone_2_init_offset (dac_dds_init_2_s),
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.tone_1_freq_word (dac_dds_init_2_s),
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.tone_2_freq_word (dac_dds_incr_2_s),
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.dac_dds_data (dac_dds_data_s));
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// single channel processor
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up_dac_channel #(
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.COMMON_ID (6'h11),
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.CHANNEL_ID(CHANNEL_ID),
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.DDS_DISABLE (0),
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.USERPORTS_DISABLE (0),
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.IQCORRECTION_DISABLE (0)
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) i_up_dac_channel (
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.dac_clk (dac_div_clk),
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.dac_rst (dac_rst),
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.dac_dds_scale_1 (dac_dds_scale_1_s),
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.dac_dds_init_1 (dac_dds_init_1_s),
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.dac_dds_incr_1 (dac_dds_incr_1_s),
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.dac_dds_scale_2 (dac_dds_scale_2_s),
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.dac_dds_init_2 (dac_dds_init_2_s),
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.dac_dds_incr_2 (dac_dds_incr_2_s),
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.dac_pat_data_1 (dac_pat_data_1_s),
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.dac_pat_data_2 (dac_pat_data_2_s),
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.dac_data_sel (dac_data_sel_s),
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.dac_iq_mode (),
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.dac_iqcor_enb (),
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.dac_iqcor_coeff_1 (),
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.dac_iqcor_coeff_2 (),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_interpolation_m (),
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.up_usr_interpolation_n (),
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.dac_usr_datatype_be (1'b0),
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.dac_usr_datatype_signed (1'b1),
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.dac_usr_datatype_shift (8'd0),
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.dac_usr_datatype_total_bits (8'd16),
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.dac_usr_datatype_bits (8'd16),
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.dac_usr_interpolation_m (16'd1),
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.dac_usr_interpolation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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