289 lines
8.1 KiB
Verilog
289 lines
8.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9684_if (
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// device interface
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adc_clk_in_p,
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adc_clk_in_n,
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adc_data_in_p,
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adc_data_in_n,
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adc_data_or_p,
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adc_data_or_n,
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// data interface
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adc_clk,
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adc_rst,
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adc_data_a,
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adc_or_a,
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adc_data_b,
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adc_or_b,
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adc_status,
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// delay interface
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delay_clk,
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delay_rst,
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delay_dload,
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delay_wdata,
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delay_rdata,
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delay_locked,
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// mmcm_rst
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mmcm_rst,
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// drp interface
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up_clk,
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up_rstn,
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up_drp_sel,
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up_drp_wr,
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up_drp_addr,
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up_drp_wdata,
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up_drp_rdata,
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up_drp_ready,
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up_drp_locked
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);
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// parameters
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parameter DEVICE_TYPE = 0; // 0 - 7Series / 1 - 6Series
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parameter IO_DELAY_GROUP = "dev_if_delay_group";
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parameter OR_STATUS = 0;
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// buffer type based on the target device
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localparam DDR_OR_SDR_N = 1;
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// IO definitions
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input adc_clk_in_p;
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input adc_clk_in_n;
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input [13:0] adc_data_in_p;
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input [13:0] adc_data_in_n;
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input adc_data_or_p;
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input adc_data_or_n;
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output adc_clk;
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input adc_rst;
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output [27:0] adc_data_a;
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output adc_or_a;
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output [27:0] adc_data_b;
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output adc_or_b;
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output adc_status;
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input delay_clk;
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input delay_rst;
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input [14:0] delay_dload;
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input [74:0] delay_wdata;
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output [74:0] delay_rdata;
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output delay_locked;
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input mmcm_rst;
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input up_clk;
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input up_rstn;
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input up_drp_sel;
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input up_drp_wr;
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input [11:0] up_drp_addr;
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input [15:0] up_drp_wdata;
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output [15:0] up_drp_rdata;
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output up_drp_ready;
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output up_drp_locked;
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// internal registers
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reg adc_status = 'd0;
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reg adc_status_m1 = 'd0;
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// internal signals
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wire adc_clk_in;
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wire adc_div_clk;
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wire [ 1:0] adc_data_or_a_s;
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wire [ 1:0] adc_data_or_b_s;
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genvar l_inst;
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// adc_clk is 1:2 of the sampling clock
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// f_max = 250 MHz
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assign adc_clk = adc_div_clk;
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// data interface
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ad_serdes_in #(
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.DEVICE_TYPE(DEVICE_TYPE),
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.IODELAY_CTRL(1),
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.IODELAY_GROUP(IO_DELAY_GROUP),
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.DDR_OR_SDR_N(DDR_OR_SDR_N),
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.DATA_WIDTH(4))
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i_adc_data (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.data_s0(adc_data_b[(1*14)]),
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.data_s1(adc_data_a[(1*14)]),
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.data_s2(adc_data_b[(0*14)]),
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.data_s3(adc_data_a[(0*14)]),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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.data_s7(),
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.data_in_p(adc_data_in_p[0]),
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.data_in_n(adc_data_in_n[0]),
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.up_clk (up_clk),
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.up_dld (delay_dload[0]),
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.up_dwdata (delay_wdata[4:0]),
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.up_drdata (delay_rdata[4:0]),
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.delay_clk(delay_clk),
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.delay_rst(delay_rst),
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.delay_locked(delay_locked));
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generate
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for (l_inst = 1; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
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ad_serdes_in #(
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.DEVICE_TYPE(DEVICE_TYPE),
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.IODELAY_CTRL(0),
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.IODELAY_GROUP(IO_DELAY_GROUP),
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.DDR_OR_SDR_N(DDR_OR_SDR_N),
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.DATA_WIDTH(4))
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i_adc_data (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.data_s0(adc_data_b[(1*14)+l_inst]),
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.data_s1(adc_data_a[(1*14)+l_inst]),
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.data_s2(adc_data_b[(0*14)+l_inst]),
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.data_s3(adc_data_a[(0*14)+l_inst]),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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.data_s7(),
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.data_in_p(adc_data_in_p[l_inst]),
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.data_in_n(adc_data_in_n[l_inst]),
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.up_clk (up_clk),
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.up_dld (delay_dload[l_inst]),
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.up_dwdata (delay_wdata[((l_inst*5)+4):(l_inst*5)]),
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.up_drdata (delay_rdata[((l_inst*5)+4):(l_inst*5)]),
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.delay_clk(delay_clk),
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.delay_rst(delay_rst),
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.delay_locked());
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end
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endgenerate
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generate if (OR_STATUS == 1) begin
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ad_serdes_in #(
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.DEVICE_TYPE(DEVICE_TYPE),
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.IODELAY_CTRL(0),
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.IODELAY_GROUP(IO_DELAY_GROUP),
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.DDR_OR_SDR_N(DDR_OR_SDR_N),
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.DATA_WIDTH(4))
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i_adc_or (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.data_s0(adc_data_or_b_s[1]),
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.data_s1(adc_data_or_a_s[1]),
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.data_s2(adc_data_or_b_s[0]),
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.data_s3(adc_data_or_a_s[0]),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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.data_s7(),
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.data_in_p(adc_data_or_p),
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.data_in_n(adc_data_or_n),
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.up_clk (up_clk),
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.up_dld (delay_dload[14]),
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.up_dwdata (delay_wdata[74:70]),
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.up_drdata (delay_rdata[74:70]),
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.delay_clk(delay_clk),
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.delay_rst(delay_rst),
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.delay_locked());
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assign adc_or_a = adc_data_or_a_s[0] | adc_data_or_a_s[1];
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assign adc_or_b = adc_data_or_b_s[0] | adc_data_or_b_s[1];
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end else begin
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assign adc_or_a = 1'b0;
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assign adc_or_b = 1'b0;
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end
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endgenerate
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// clock input buffers and MMCM_OR_BUFR_N
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ad_serdes_clk #(
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.MMCM_DEVICE_TYPE (DEVICE_TYPE),
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.MMCM_CLKIN_PERIOD (2),
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.MMCM_VCO_DIV (6),
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.MMCM_VCO_MUL (12),
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.MMCM_CLK0_DIV (2),
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.MMCM_CLK1_DIV (4))
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i_serdes_clk (
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.mmcm_rst (mmcm_rst),
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.clk_in_p (adc_clk_in_p),
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.clk_in_n (adc_clk_in_n),
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.clk (adc_clk_in),
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.div_clk (adc_div_clk),
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.out_clk (),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_drp_sel (up_drp_sel),
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.up_drp_wr (up_drp_wr),
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.up_drp_addr (up_drp_addr),
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.up_drp_wdata (up_drp_wdata),
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.up_drp_rdata (up_drp_rdata),
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.up_drp_ready (up_drp_ready),
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.up_drp_locked (up_drp_locked));
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// adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up
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always @(posedge adc_div_clk) begin
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if(adc_rst == 1'b1) begin
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adc_status_m1 <= 1'b0;
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adc_status <= 1'b0;
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end else begin
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adc_status_m1 <= up_drp_locked;
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adc_status <= adc_status_m1;
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end
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end
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endmodule
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