558f2e89af
The toplevel input/output signal names are lower case, but the signals connected to the system_wrapper are upper case. Since verilog is case sensitive this leaves the toplevel input/output signals unconnected. Fix this by using lower case names everywhere. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| common | ||
| zc706 | ||
| zed | ||
| Makefile | ||