369 lines
12 KiB
Verilog
369 lines
12 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_dac_channel (
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// dac interface
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dac_clk,
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dac_rst,
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dac_dds_scale_1,
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dac_dds_init_1,
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dac_dds_incr_1,
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dac_dds_scale_2,
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dac_dds_init_2,
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dac_dds_incr_2,
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dac_pat_data_1,
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dac_pat_data_2,
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dac_data_sel,
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dac_iqcor_enb,
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dac_iqcor_coeff_1,
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dac_iqcor_coeff_2,
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// user controls
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up_usr_datatype_be,
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up_usr_datatype_signed,
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up_usr_datatype_shift,
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up_usr_datatype_total_bits,
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up_usr_datatype_bits,
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up_usr_interpolation_m,
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up_usr_interpolation_n,
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dac_usr_datatype_be,
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dac_usr_datatype_signed,
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dac_usr_datatype_shift,
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dac_usr_datatype_total_bits,
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dac_usr_datatype_bits,
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dac_usr_interpolation_m,
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dac_usr_interpolation_n,
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// bus interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack);
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// parameters
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parameter DAC_COMMON_ID = 6'h11;
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parameter DAC_CHANNEL_ID = 4'h0;
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// dac interface
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input dac_clk;
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input dac_rst;
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output [15:0] dac_dds_scale_1;
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output [15:0] dac_dds_init_1;
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output [15:0] dac_dds_incr_1;
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output [15:0] dac_dds_scale_2;
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output [15:0] dac_dds_init_2;
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output [15:0] dac_dds_incr_2;
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output [15:0] dac_pat_data_1;
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output [15:0] dac_pat_data_2;
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output [ 3:0] dac_data_sel;
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output dac_iqcor_enb;
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output [15:0] dac_iqcor_coeff_1;
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output [15:0] dac_iqcor_coeff_2;
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// user controls
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output up_usr_datatype_be;
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output up_usr_datatype_signed;
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output [ 7:0] up_usr_datatype_shift;
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output [ 7:0] up_usr_datatype_total_bits;
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output [ 7:0] up_usr_datatype_bits;
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output [15:0] up_usr_interpolation_m;
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output [15:0] up_usr_interpolation_n;
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input dac_usr_datatype_be;
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input dac_usr_datatype_signed;
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input [ 7:0] dac_usr_datatype_shift;
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input [ 7:0] dac_usr_datatype_total_bits;
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input [ 7:0] dac_usr_datatype_bits;
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input [15:0] dac_usr_interpolation_m;
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input [15:0] dac_usr_interpolation_n;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_rack;
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// internal registers
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reg up_wack = 'd0;
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reg [15:0] up_dac_dds_scale_1 = 'd0;
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reg [15:0] up_dac_dds_init_1 = 'd0;
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reg [15:0] up_dac_dds_incr_1 = 'd0;
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reg [15:0] up_dac_dds_scale_2 = 'd0;
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reg [15:0] up_dac_dds_init_2 = 'd0;
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reg [15:0] up_dac_dds_incr_2 = 'd0;
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reg [15:0] up_dac_pat_data_2 = 'd0;
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reg [15:0] up_dac_pat_data_1 = 'd0;
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reg up_dac_iqcor_enb = 'd0;
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reg up_dac_lb_enb = 'd0;
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reg up_dac_pn_enb = 'd0;
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reg [ 3:0] up_dac_data_sel = 'd0;
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reg [15:0] up_dac_iqcor_coeff_1 = 'd0;
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reg [15:0] up_dac_iqcor_coeff_2 = 'd0;
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reg up_usr_datatype_be = 'd0;
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reg up_usr_datatype_signed = 'd0;
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reg [ 7:0] up_usr_datatype_shift = 'd0;
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reg [ 7:0] up_usr_datatype_total_bits = 'd0;
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reg [ 7:0] up_usr_datatype_bits = 'd0;
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reg [15:0] up_usr_interpolation_m = 'd0;
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reg [15:0] up_usr_interpolation_n = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg [15:0] up_dac_dds_scale_tc_1 = 'd0;
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reg [15:0] up_dac_dds_scale_tc_2 = 'd0;
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reg [15:0] up_dac_iqcor_coeff_tc_1 = 'd0;
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reg [15:0] up_dac_iqcor_coeff_tc_2 = 'd0;
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reg [ 3:0] up_dac_data_sel_m = 'd0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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// 2's complement function
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function [15:0] sm2tc;
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input [15:0] din;
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reg [15:0] dp;
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reg [15:0] dn;
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reg [15:0] dout;
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begin
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dp = {1'b0, din[14:0]};
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dn = ~dp + 1'b1;
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dout = (din[15] == 1'b1) ? dn : dp;
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sm2tc = dout;
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end
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endfunction
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// decode block select
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assign up_wreq_s = ((up_waddr[13:8] == DAC_COMMON_ID) && (up_waddr[7:4] == DAC_CHANNEL_ID)) ? up_wreq : 1'b0;
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assign up_rreq_s = ((up_raddr[13:8] == DAC_COMMON_ID) && (up_raddr[7:4] == DAC_CHANNEL_ID)) ? up_rreq : 1'b0;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_dac_dds_scale_1 <= 'd0;
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up_dac_dds_init_1 <= 'd0;
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up_dac_dds_incr_1 <= 'd0;
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up_dac_dds_scale_2 <= 'd0;
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up_dac_dds_init_2 <= 'd0;
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up_dac_dds_incr_2 <= 'd0;
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up_dac_pat_data_2 <= 'd0;
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up_dac_pat_data_1 <= 'd0;
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up_dac_iqcor_enb <= 'd0;
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up_dac_lb_enb <= 'd0;
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up_dac_pn_enb <= 'd0;
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up_dac_data_sel <= 'd0;
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up_dac_iqcor_coeff_1 <= 'd0;
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up_dac_iqcor_coeff_2 <= 'd0;
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up_usr_datatype_be <= 'd0;
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up_usr_datatype_signed <= 'd0;
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up_usr_datatype_shift <= 'd0;
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up_usr_datatype_total_bits <= 'd0;
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up_usr_datatype_bits <= 'd0;
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up_usr_interpolation_m <= 'd0;
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up_usr_interpolation_n <= 'd0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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up_dac_dds_scale_1 <= up_wdata[15:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
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up_dac_dds_init_1 <= up_wdata[31:16];
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up_dac_dds_incr_1 <= up_wdata[15:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h2)) begin
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up_dac_dds_scale_2 <= up_wdata[15:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h3)) begin
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up_dac_dds_init_2 <= up_wdata[31:16];
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up_dac_dds_incr_2 <= up_wdata[15:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin
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up_dac_pat_data_2 <= up_wdata[31:16];
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up_dac_pat_data_1 <= up_wdata[15:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
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up_dac_iqcor_enb <= up_wdata[2];
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up_dac_lb_enb <= up_wdata[1];
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up_dac_pn_enb <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin
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up_dac_data_sel <= up_wdata[3:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h7)) begin
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up_dac_iqcor_coeff_1 <= up_wdata[31:16];
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up_dac_iqcor_coeff_2 <= up_wdata[15:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin
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up_usr_datatype_be <= up_wdata[25];
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up_usr_datatype_signed <= up_wdata[24];
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up_usr_datatype_shift <= up_wdata[23:16];
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up_usr_datatype_total_bits <= up_wdata[15:8];
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up_usr_datatype_bits <= up_wdata[7:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin
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up_usr_interpolation_m <= up_wdata[31:16];
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up_usr_interpolation_n <= up_wdata[15:0];
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[3:0])
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4'h0: up_rdata <= {16'd0, up_dac_dds_scale_1};
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4'h1: up_rdata <= {up_dac_dds_init_1, up_dac_dds_incr_1};
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4'h2: up_rdata <= {16'd0, up_dac_dds_scale_2};
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4'h3: up_rdata <= {up_dac_dds_init_2, up_dac_dds_incr_2};
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4'h4: up_rdata <= {up_dac_pat_data_2, up_dac_pat_data_1};
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4'h5: up_rdata <= {29'd0, up_dac_iqcor_enb, up_dac_lb_enb, up_dac_pn_enb};
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4'h6: up_rdata <= {28'd0, up_dac_data_sel_m};
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4'h7: up_rdata <= {up_dac_iqcor_coeff_1, up_dac_iqcor_coeff_2};
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4'h8: up_rdata <= {6'd0, dac_usr_datatype_be, dac_usr_datatype_signed,
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dac_usr_datatype_shift, dac_usr_datatype_total_bits,
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dac_usr_datatype_bits};
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4'h9: up_rdata <= {dac_usr_interpolation_m, dac_usr_interpolation_n};
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// change coefficients to 2's complements
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_dac_dds_scale_tc_1 <= 16'd0;
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up_dac_dds_scale_tc_2 <= 16'd0;
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up_dac_iqcor_coeff_tc_1 <= 16'd0;
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up_dac_iqcor_coeff_tc_2 <= 16'd0;
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end else begin
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up_dac_dds_scale_tc_1 <= sm2tc(up_dac_dds_scale_1);
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up_dac_dds_scale_tc_2 <= sm2tc(up_dac_dds_scale_2);
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up_dac_iqcor_coeff_tc_1 <= sm2tc(up_dac_iqcor_coeff_1);
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up_dac_iqcor_coeff_tc_2 <= sm2tc(up_dac_iqcor_coeff_2);
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end
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end
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// backward compatibility
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_dac_data_sel_m <= 4'd0;
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end else begin
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case ({up_dac_lb_enb, up_dac_pn_enb})
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2'b10: up_dac_data_sel_m <= 4'h8;
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2'b01: up_dac_data_sel_m <= 4'h9;
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default: up_dac_data_sel_m <= up_dac_data_sel;
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endcase
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end
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end
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// dac control & status
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up_xfer_cntrl #(.DATA_WIDTH(165)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_dac_iqcor_enb,
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up_dac_iqcor_coeff_tc_1,
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up_dac_iqcor_coeff_tc_2,
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up_dac_dds_scale_tc_1,
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up_dac_dds_init_1,
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up_dac_dds_incr_1,
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up_dac_dds_scale_tc_2,
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up_dac_dds_init_2,
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up_dac_dds_incr_2,
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up_dac_pat_data_1,
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up_dac_pat_data_2,
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up_dac_data_sel_m}),
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.up_xfer_done (),
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.d_rst (dac_rst),
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.d_clk (dac_clk),
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.d_data_cntrl ({ dac_iqcor_enb,
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dac_iqcor_coeff_1,
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dac_iqcor_coeff_2,
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dac_dds_scale_1,
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dac_dds_init_1,
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dac_dds_incr_1,
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dac_dds_scale_2,
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dac_dds_init_2,
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dac_dds_incr_2,
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dac_pat_data_1,
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dac_pat_data_2,
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dac_data_sel}));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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