345 lines
10 KiB
Verilog
345 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_xcvr (
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// common reset
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rst,
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// receive interface
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rx_clk,
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rx_rstn,
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rx_ext_sysref,
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rx_sysref,
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rx_ip_sync,
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rx_sync,
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rx_status,
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// transmit interface
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tx_clk,
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tx_rstn,
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tx_ext_sysref,
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tx_sysref,
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tx_sync,
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tx_ip_sync,
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tx_status,
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// bus interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack);
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// parameters
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localparam PCORE_VERSION = 32'h00060162;
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parameter ID = 0;
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parameter DEVICE_TYPE = 0;
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// common reset
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output rst;
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// receive interface
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input rx_clk;
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output rx_rstn;
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input rx_ext_sysref;
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output rx_sysref;
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input rx_ip_sync;
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output rx_sync;
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input [ 7:0] rx_status;
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// transmit interface
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input tx_clk;
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output tx_rstn;
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input tx_ext_sysref;
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output tx_sysref;
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input tx_sync;
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output tx_ip_sync;
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input [ 7:0] tx_status;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_rack;
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// internal registers
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reg up_reset = 'd1;
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reg up_rx_reset = 'd1;
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reg up_tx_reset = 'd1;
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reg up_wack = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_resetn = 'd0;
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reg up_rx_sysref_sel = 'd0;
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reg up_rx_sysref = 'd0;
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reg up_rx_sync = 'd0;
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reg up_rx_resetn = 'd0;
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reg up_tx_sysref_sel = 'd0;
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reg up_tx_sysref = 'd0;
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reg up_tx_sync = 'd0;
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reg up_tx_resetn = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg rx_rstn = 'd0;
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reg rx_sysref_sel_m1 = 'd0;
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reg rx_sysref_sel = 'd0;
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reg rx_up_sysref_m1 = 'd0;
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reg rx_up_sysref = 'd0;
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reg rx_sysref = 'd0;
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reg rx_up_sync_m1 = 'd0;
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reg rx_up_sync = 'd0;
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reg rx_sync = 'd0;
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reg tx_rstn = 'd0;
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reg tx_sysref_sel_m1 = 'd0;
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reg tx_sysref_sel = 'd0;
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reg tx_up_sysref_m1 = 'd0;
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reg tx_up_sysref = 'd0;
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reg tx_sysref = 'd0;
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reg tx_up_sync_m1 = 'd0;
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reg tx_up_sync = 'd0;
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reg tx_ip_sync = 'd0;
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reg [ 8:0] up_rx_status_m1 = 'd0;
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reg [ 8:0] up_rx_status = 'd0;
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reg [ 8:0] up_tx_status_m1 = 'd0;
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reg [ 8:0] up_tx_status = 'd0;
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// internal signals
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wire rx_rst;
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wire tx_rst;
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wire up_wreq_s;
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wire up_rreq_s;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_reset <= 1'b1;
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up_rx_reset <= 1'b1;
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up_tx_reset <= 1'b1;
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_resetn <= 'd0;
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up_rx_sysref_sel <= 'd0;
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up_rx_sysref <= 'd0;
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up_rx_sync <= 'd0;
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up_rx_resetn <= 'd0;
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up_tx_sysref_sel <= 'd0;
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up_tx_sysref <= 'd0;
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up_tx_sync <= 'd0;
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up_tx_resetn <= 'd0;
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end else begin
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up_reset <= ~up_resetn;
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up_rx_reset <= ~(up_resetn & up_rx_resetn);
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up_tx_reset <= ~(up_resetn & up_tx_resetn);
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h03)) begin
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up_resetn <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
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up_rx_sysref_sel <= up_wdata[1];
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up_rx_sysref <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
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up_rx_sync <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
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up_rx_resetn <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
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up_tx_sysref_sel <= up_wdata[1];
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up_tx_sysref <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
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up_tx_sync <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
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up_tx_resetn <= up_wdata[0];
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h00: up_rdata <= PCORE_VERSION;
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8'h01: up_rdata <= ID;
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8'h02: up_rdata <= up_scratch;
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8'h03: up_rdata <= {31'd0, up_resetn};
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8'h10: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref};
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8'h11: up_rdata <= {31'd0, up_rx_sync};
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8'h12: up_rdata <= {23'd0, up_rx_status};
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8'h13: up_rdata <= {31'd0, up_rx_resetn};
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8'h20: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref};
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8'h21: up_rdata <= {31'd0, up_tx_sync};
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8'h22: up_rdata <= {23'd0, up_tx_status};
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8'h23: up_rdata <= {31'd0, up_tx_resetn};
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8'h30: up_rdata <= DEVICE_TYPE;
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// resets
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assign rst = up_reset;
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ad_rst i_rx_rst_reg (.preset(up_rx_reset), .clk(rx_clk), .rst(rx_rst));
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ad_rst i_tx_rst_reg (.preset(up_tx_reset), .clk(tx_clk), .rst(tx_rst));
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// rx sysref & sync
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always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst == 1'b1) begin
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rx_rstn <= 'd0;
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rx_sysref_sel_m1 <= 'd0;
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rx_sysref_sel <= 'd0;
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rx_up_sysref_m1 <= 'd0;
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rx_up_sysref <= 'd0;
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rx_sysref <= 'd0;
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rx_up_sync_m1 <= 'd0;
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rx_up_sync <= 'd0;
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rx_sync <= 'd0;
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end else begin
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rx_rstn <= 1'd1;
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rx_sysref_sel_m1 <= up_rx_sysref_sel;
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rx_sysref_sel <= rx_sysref_sel_m1;
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rx_up_sysref_m1 <= up_rx_sysref;
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rx_up_sysref <= rx_up_sysref_m1;
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if (rx_sysref_sel == 1'b1) begin
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rx_sysref <= rx_ext_sysref;
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end else begin
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rx_sysref <= rx_up_sysref;
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end
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rx_up_sync_m1 <= up_rx_sync;
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rx_up_sync <= rx_up_sync_m1;
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rx_sync <= rx_up_sync & rx_ip_sync;
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end
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end
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// tx sysref & sync
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always @(posedge tx_clk or posedge tx_rst) begin
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if (tx_rst == 1'b1) begin
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tx_rstn <= 'd0;
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tx_sysref_sel_m1 <= 'd0;
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tx_sysref_sel <= 'd0;
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tx_up_sysref_m1 <= 'd0;
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tx_up_sysref <= 'd0;
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tx_sysref <= 'd0;
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tx_up_sync_m1 <= 'd0;
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tx_up_sync <= 'd0;
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tx_ip_sync <= 'd0;
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end else begin
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tx_rstn <= 1'd1;
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tx_sysref_sel_m1 <= up_tx_sysref_sel;
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tx_sysref_sel <= tx_sysref_sel_m1;
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tx_up_sysref_m1 <= up_tx_sysref;
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tx_up_sysref <= tx_up_sysref_m1;
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if (tx_sysref_sel == 1'b1) begin
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tx_sysref <= tx_ext_sysref;
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end else begin
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tx_sysref <= tx_up_sysref;
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end
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tx_up_sync_m1 <= up_tx_sync;
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tx_up_sync <= tx_up_sync_m1;
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tx_ip_sync <= tx_up_sync & tx_sync;
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end
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end
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// status
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rx_status_m1 <= 'd0;
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up_rx_status <= 'd0;
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up_tx_status_m1 <= 'd0;
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up_tx_status <= 'd0;
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end else begin
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up_rx_status_m1 <= {rx_sync, rx_status};
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up_rx_status <= up_rx_status_m1;
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up_tx_status_m1 <= {tx_ip_sync, tx_status};
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up_tx_status <= up_tx_status_m1;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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