55daa786fa
Add missing timing exceptions on paths between the DMA and DDR clock domains. All these paths are properly synchronized using CDC in the HDL, but are missing timing exceptions in the XDC file. This can lead to timing errors when building a design using the axi_adc_fifo. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| axi_adcfifo | ||
| axi_adxcvr | ||
| axi_dacfifo | ||
| axi_xcvrlb | ||
| common | ||
| util_adxcvr | ||