516 lines
17 KiB
Verilog
516 lines
17 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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sys_clk,
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// hps
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ddr3_a,
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ddr3_ba,
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ddr3_ck_p,
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ddr3_ck_n,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_ras_n,
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ddr3_cas_n,
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ddr3_we_n,
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ddr3_reset_n,
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ddr3_dq,
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ddr3_dqs_p,
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ddr3_dqs_n,
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ddr3_odt,
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ddr3_dm,
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ddr3_oct_rzqin,
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eth1_tx_clk,
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eth1_tx_ctl,
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eth1_txd0,
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eth1_txd1,
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eth1_txd2,
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eth1_txd3,
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eth1_rx_clk,
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eth1_rx_ctl,
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eth1_rxd0,
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eth1_rxd1,
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eth1_rxd2,
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eth1_rxd3,
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eth1_mdc,
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eth1_mdio,
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qspi_ss0,
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qspi_clk,
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qspi_io0,
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qspi_io1,
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qspi_io2,
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qspi_io3,
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sdio_clk,
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sdio_cmd,
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sdio_d0,
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sdio_d1,
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sdio_d2,
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sdio_d3,
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usb1_clk,
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usb1_stp,
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usb1_dir,
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usb1_nxt,
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usb1_d0,
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usb1_d1,
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usb1_d2,
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usb1_d3,
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usb1_d4,
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usb1_d5,
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usb1_d6,
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usb1_d7,
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spim1_ss0,
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spim1_clk,
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spim1_mosi,
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spim1_miso,
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uart0_rx,
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uart0_tx,
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// board gpio
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led,
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push_buttons,
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dip_switches,
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// display
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vga_clk,
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vga_blank_n,
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vga_sync_n,
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vga_hs,
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vga_vs,
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vga_r,
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vga_g,
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vga_b,
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// data interface
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rx_clk_in,
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rx_frame_in,
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rx_data_in,
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tx_clk_out,
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tx_frame_out,
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tx_data_out,
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// gpio interface
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ad9361_resetb,
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// spi
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso);
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// clock and resets
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input sys_clk;
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// hps
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output [ 14:0] ddr3_a;
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output [ 2:0] ddr3_ba;
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output ddr3_ck_p;
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output ddr3_ck_n;
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output ddr3_cke;
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output ddr3_cs_n;
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output ddr3_ras_n;
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output ddr3_cas_n;
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output ddr3_we_n;
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output ddr3_reset_n;
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inout [ 31:0] ddr3_dq;
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inout [ 3:0] ddr3_dqs_p;
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inout [ 3:0] ddr3_dqs_n;
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output ddr3_odt;
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output [ 3:0] ddr3_dm;
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input ddr3_oct_rzqin;
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output eth1_tx_clk;
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output eth1_tx_ctl;
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output eth1_txd0;
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output eth1_txd1;
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output eth1_txd2;
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output eth1_txd3;
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input eth1_rx_clk;
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input eth1_rx_ctl;
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input eth1_rxd0;
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input eth1_rxd1;
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input eth1_rxd2;
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input eth1_rxd3;
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output eth1_mdc;
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inout eth1_mdio;
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output qspi_ss0;
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output qspi_clk;
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inout qspi_io0;
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inout qspi_io1;
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inout qspi_io2;
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inout qspi_io3;
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output sdio_clk;
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inout sdio_cmd;
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inout sdio_d0;
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inout sdio_d1;
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inout sdio_d2;
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inout sdio_d3;
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input usb1_clk;
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output usb1_stp;
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input usb1_dir;
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input usb1_nxt;
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inout usb1_d0;
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inout usb1_d1;
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inout usb1_d2;
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inout usb1_d3;
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inout usb1_d4;
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inout usb1_d5;
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inout usb1_d6;
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inout usb1_d7;
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output spim1_ss0;
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output spim1_clk;
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output spim1_mosi;
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input spim1_miso;
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input uart0_rx;
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output uart0_tx;
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// board gpio
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output [ 3:0] led;
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input [ 3:0] push_buttons;
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input [ 3:0] dip_switches;
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// display
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output vga_clk;
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output vga_blank_n;
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output vga_sync_n;
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output vga_hs;
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output vga_vs;
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output [ 7:0] vga_r;
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output [ 7:0] vga_g;
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output [ 7:0] vga_b;
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// data interface
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input rx_clk_in;
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input rx_frame_in;
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input [ 5:0] rx_data_in;
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output tx_clk_out;
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output tx_frame_out;
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output [ 5:0] tx_data_out;
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// gpio interface
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output ad9361_resetb;
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// spi interface
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output spi_csn;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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// internal clocks and resets
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wire [ 31:0] gpio_open;
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wire sys_resetn;
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wire clk;
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// internal signals
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wire adc_enable_i0;
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wire adc_enable_q0;
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wire adc_enable_i1;
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wire adc_enable_q1;
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wire adc_valid_i0;
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wire adc_valid_q0;
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wire adc_valid_i1;
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wire adc_valid_q1;
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wire adc_dwr;
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wire adc_dsync;
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wire [ 15:0] adc_chan_i0;
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wire [ 15:0] adc_chan_q0;
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wire [ 15:0] adc_chan_i1;
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wire [ 15:0] adc_chan_q1;
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wire [ 63:0] adc_ddata;
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wire adc_dovf;
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wire dac_enable_i0;
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wire dac_enable_q0;
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wire dac_enable_i1;
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wire dac_enable_q1;
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wire dac_valid_i0;
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wire dac_valid_q0;
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wire dac_valid_i1;
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wire dac_valid_q1;
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wire [ 15:0] dac_data_i0;
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wire [ 15:0] dac_data_q0;
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wire [ 15:0] dac_data_i1;
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wire [ 15:0] dac_data_q1;
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wire [ 63:0] dac_ddata;
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wire dac_dunf;
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wire dac_rd_en;
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wire dac_fifo_valid;
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wire [111:0] dev_dbg_data;
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wire [ 61:0] dev_l_dbg_data;
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wire vga_pixel_clock;
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wire vid_v_sync;
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wire vid_h_sync;
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wire [7:0] vid_r,vid_g,vid_b;
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// defaults
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assign vga_clk = vga_pixel_clock;
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assign vga_blank_n = 1'b1;
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assign vga_sync_n = 1'b0;
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assign vga_hs = vid_h_sync;
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assign vga_vs = vid_v_sync;
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assign {vga_b,vga_g,vga_r} = {vid_b,vid_g,vid_r};
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assign ad9361_resetb = 1'b1;
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// instantiations
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sld_signaltap #(
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.sld_advanced_trigger_entity ("basic,1,"),
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.sld_data_bits (64),
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.sld_data_bit_cntr_bits (7),
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.sld_enable_advanced_trigger (0),
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.sld_mem_address_bits (10),
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.sld_node_crc_bits (32),
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.sld_node_crc_hiword (13323),
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.sld_node_crc_loword (24084),
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.sld_node_info (1076736),
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.sld_ram_block_type ("AUTO"),
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.sld_sample_depth (1024),
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.sld_storage_qualifier_gap_record (0),
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.sld_storage_qualifier_mode ("OFF"),
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.sld_trigger_bits (1),
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.sld_trigger_in_enabled (0),
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.sld_trigger_level (1),
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.sld_trigger_level_pipeline (1))
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i_ila_adc (
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.acq_clk (clk),
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.acq_data_in (adc_ddata),
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.acq_trigger_in (adc_valid_i0));
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system_bd i_system_bd (
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.clk_clk (sys_clk),
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.reset_reset_n (sys_resetn),
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.sys_hps_memory_mem_a (ddr3_a),
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.sys_hps_memory_mem_ba (ddr3_ba),
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.sys_hps_memory_mem_ck (ddr3_ck_p),
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.sys_hps_memory_mem_ck_n (ddr3_ck_n),
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.sys_hps_memory_mem_cke (ddr3_cke),
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.sys_hps_memory_mem_cs_n (ddr3_cs_n),
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.sys_hps_memory_mem_ras_n (ddr3_ras_n),
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.sys_hps_memory_mem_cas_n (ddr3_cas_n),
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.sys_hps_memory_mem_we_n (ddr3_we_n),
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.sys_hps_memory_mem_reset_n (ddr3_reset_n),
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.sys_hps_memory_mem_dq (ddr3_dq),
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.sys_hps_memory_mem_dqs (ddr3_dqs_p),
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.sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
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.sys_hps_memory_mem_odt (ddr3_odt),
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.sys_hps_memory_mem_dm (ddr3_dm),
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.sys_hps_memory_oct_rzqin (ddr3_oct_rzqin),
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.sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
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.sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
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.sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
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.sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
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.sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
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.sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
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.sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
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.sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
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.sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
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.sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
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.sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
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.sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
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.sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
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.sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
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.sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
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.sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
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.sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
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.sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
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.sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
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.sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
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.sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
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.sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d0),
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.sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d1),
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.sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
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.sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d2),
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.sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d3),
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.sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d0),
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.sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d1),
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.sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d2),
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.sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d3),
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.sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d4),
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.sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d5),
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.sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d6),
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.sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d7),
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.sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
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.sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
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.sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
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.sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
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.sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
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.sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
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.sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
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.sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
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.sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
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.sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
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.sys_gpio_external_connection_in_port ({16'd0, 4'd0, led, push_buttons, dip_switches}),
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.sys_gpio_external_connection_out_port ({gpio_open[31:16], gpio_open[15:12], led, gpio_open[7:0]}),
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.sys_hps_h2f_reset_reset_n (sys_resetn),
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.sys_hps_spim0_txd (),
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.sys_hps_spim0_rxd (),
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.sys_hps_spim0_ss_in_n (1'b1),
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.sys_hps_spim0_ssi_oe_n (),
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.sys_hps_spim0_ss_0_n (),
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.sys_hps_spim0_ss_1_n (),
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.sys_hps_spim0_ss_2_n (),
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.sys_hps_spim0_ss_3_n (),
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.sys_hps_spim0_sclk_out_clk (),
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.axi_ad9361_device_clock_clk (clk),
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.axi_ad9361_device_if_rx_clk_in_p (rx_clk_in),
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.axi_ad9361_device_if_rx_clk_in_n (1'b0),
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.axi_ad9361_device_if_rx_frame_in_p (rx_frame_in),
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.axi_ad9361_device_if_rx_frame_in_n (1'b0),
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.axi_ad9361_device_if_rx_data_in_p (rx_data_in),
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.axi_ad9361_device_if_rx_data_in_n (6'd0),
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.axi_ad9361_device_if_tx_clk_out_p (tx_clk_out),
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.axi_ad9361_device_if_tx_clk_out_n (),
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.axi_ad9361_device_if_tx_frame_out_p (tx_frame_out),
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.axi_ad9361_device_if_tx_frame_out_n (),
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.axi_ad9361_device_if_tx_data_out_p (tx_data_out),
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.axi_ad9361_device_if_tx_data_out_n (),
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.axi_ad9361_master_if_l_clk (clk),
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.axi_ad9361_master_if_dac_sync_in (1'b0),
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.axi_ad9361_master_if_dac_sync_out (),
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.axi_ad9361_dma_if_adc_enable_i0 (adc_enable_i0),
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.axi_ad9361_dma_if_adc_valid_i0 (adc_valid_i0),
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.axi_ad9361_dma_if_adc_data_i0 (adc_chan_i0),
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.axi_ad9361_dma_if_adc_enable_q0 (adc_enable_q0),
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.axi_ad9361_dma_if_adc_valid_q0 (adc_valid_q0),
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.axi_ad9361_dma_if_adc_data_q0 (adc_chan_q0),
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.axi_ad9361_dma_if_adc_enable_i1 (adc_enable_i1),
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.axi_ad9361_dma_if_adc_valid_i1 (adc_valid_i1),
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.axi_ad9361_dma_if_adc_data_i1 (adc_chan_i1),
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.axi_ad9361_dma_if_adc_enable_q1 (adc_enable_q1),
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.axi_ad9361_dma_if_adc_valid_q1 (adc_valid_q1),
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.axi_ad9361_dma_if_adc_data_q1 (adc_chan_q1),
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.axi_ad9361_dma_if_adc_dovf (adc_dovf),
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.axi_ad9361_dma_if_adc_dunf (),
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.axi_ad9361_dma_if_dac_enable_i0 (dac_enable_i0),
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.axi_ad9361_dma_if_dac_valid_i0 (dac_valid_i0),
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|
.axi_ad9361_dma_if_dac_data_i0 (dac_data_i0),
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|
.axi_ad9361_dma_if_dac_enable_q0 (dac_enable_q0),
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.axi_ad9361_dma_if_dac_valid_q0 (dac_valid_q0),
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|
.axi_ad9361_dma_if_dac_data_q0 (dac_data_q0),
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|
.axi_ad9361_dma_if_dac_enable_i1 (dac_enable_i1),
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|
.axi_ad9361_dma_if_dac_valid_i1 (dac_valid_i1),
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|
.axi_ad9361_dma_if_dac_data_i1 (dac_data_i1),
|
|
.axi_ad9361_dma_if_dac_enable_q1 (dac_enable_q1),
|
|
.axi_ad9361_dma_if_dac_valid_q1 (dac_valid_q1),
|
|
.axi_ad9361_dma_if_dac_data_q1 (dac_data_q1),
|
|
.axi_ad9361_dma_if_dac_dovf (),
|
|
.axi_ad9361_dma_if_dac_dunf (dac_dunf),
|
|
.axi_ad9361_debug_if_dev_dbg_data (dev_dbg_data),
|
|
.axi_ad9361_debug_if_dev_l_dbg_data (dev_l_dbg_data),
|
|
.axi_dmac_dac_fifo_rd_clock_clk (clk),
|
|
.axi_dmac_dac_fifo_rd_if_rden (dac_rd_en),
|
|
.axi_dmac_dac_fifo_rd_if_valid (dac_fifo_valid),
|
|
.axi_dmac_dac_fifo_rd_if_data (dac_ddata),
|
|
.axi_dmac_dac_fifo_rd_if_unf (dac_dunf),
|
|
.axi_dmac_adc_fifo_wr_clock_clk (clk),
|
|
.axi_dmac_adc_fifo_wr_if_ovf (adc_dovf),
|
|
.axi_dmac_adc_fifo_wr_if_wren (adc_dwr),
|
|
.axi_dmac_adc_fifo_wr_if_data (adc_ddata),
|
|
.axi_dmac_adc_fifo_wr_if_sync (adc_dsync),
|
|
.spi_ad9361_external_MISO (spi_miso),
|
|
.spi_ad9361_external_MOSI (spi_mosi),
|
|
.spi_ad9361_external_SCLK (spi_clk),
|
|
.spi_ad9361_external_SS_n (spi_csn),
|
|
.vga_pixel_clock_bridge_out_clk_clk (vga_pixel_clock),
|
|
.vga_clock_video_output_clocked_video_vid_clk (vga_pixel_clock),
|
|
.vga_clock_video_output_clocked_video_vid_data ({vid_r,vid_g,vid_b}),
|
|
.vga_clock_video_output_clocked_video_underflow (),
|
|
.vga_clock_video_output_clocked_video_vid_datavalid (),
|
|
.vga_clock_video_output_clocked_video_vid_v_sync (vid_v_sync),
|
|
.vga_clock_video_output_clocked_video_vid_h_sync (vid_h_sync),
|
|
.vga_clock_video_output_clocked_video_vid_f (),
|
|
.vga_clock_video_output_clocked_video_vid_h (),
|
|
.vga_clock_video_output_clocked_video_vid_v (),
|
|
.adc_pack_data_clock_clk (clk),
|
|
.adc_pack_channels_data_chan_enable_0 (adc_enable_i0),
|
|
.adc_pack_channels_data_chan_valid_0 (adc_valid_i0),
|
|
.adc_pack_channels_data_chan_data_0 (adc_chan_i0),
|
|
.adc_pack_channels_data_chan_enable_1 (adc_enable_q0),
|
|
.adc_pack_channels_data_chan_valid_1 (adc_valid_q0),
|
|
.adc_pack_channels_data_chan_data_1 (adc_chan_q0),
|
|
.adc_pack_channels_data_chan_enable_2 (adc_enable_i1),
|
|
.adc_pack_channels_data_chan_valid_2 (adc_valid_i1),
|
|
.adc_pack_channels_data_chan_data_2 (adc_chan_i1),
|
|
.adc_pack_channels_data_chan_enable_3 (adc_enable_q1),
|
|
.adc_pack_channels_data_chan_valid_3 (adc_valid_q1),
|
|
.adc_pack_channels_data_chan_data_3 (adc_chan_q1),
|
|
.adc_pack_channels_data_dvalid (adc_dwr),
|
|
.adc_pack_channels_data_dsync (adc_dsync),
|
|
.adc_pack_channels_data_ddata (adc_ddata),
|
|
.util_dac_unpack_data_clock_clk (clk),
|
|
.util_dac_unpack_channels_data_dac_enable_00 (dac_enable_i0),
|
|
.util_dac_unpack_channels_data_dac_valid_00 (dac_valid_i0),
|
|
.util_dac_unpack_channels_data_dac_data_00 (dac_data_i0),
|
|
.util_dac_unpack_channels_data_dac_enable_01 (dac_enable_q0),
|
|
.util_dac_unpack_channels_data_dac_valid_01 (dac_valid_q0),
|
|
.util_dac_unpack_channels_data_dac_data_01 (dac_data_q0),
|
|
.util_dac_unpack_channels_data_dac_enable_02 (dac_enable_i1),
|
|
.util_dac_unpack_channels_data_dac_valid_02 (dac_valid_i1),
|
|
.util_dac_unpack_channels_data_dac_data_02 (dac_data_i1),
|
|
.util_dac_unpack_channels_data_dac_enable_03 (dac_enable_q1),
|
|
.util_dac_unpack_channels_data_dac_valid_03 (dac_valid_q1),
|
|
.util_dac_unpack_channels_data_dac_data_03 (dac_data_q1),
|
|
.util_dac_unpack_channels_data_fifo_valid (dac_fifo_valid),
|
|
.util_dac_unpack_channels_data_dma_rd (dac_rd_en),
|
|
.util_dac_unpack_channels_data_dma_data (dac_ddata)
|
|
);
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
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