302 lines
8.6 KiB
Verilog
302 lines
8.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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sys_clk,
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sys_resetn,
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// ddr3
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ddr3_clk_p,
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ddr3_clk_n,
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ddr3_a,
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ddr3_ba,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_odt,
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ddr3_reset_n,
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ddr3_we_n,
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ddr3_ras_n,
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ddr3_cas_n,
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ddr3_dqs_p,
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ddr3_dqs_n,
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ddr3_dq,
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ddr3_dm,
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ddr3_rzq,
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ddr3_ref_clk,
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// ethernet
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eth_ref_clk,
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eth_rxd,
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eth_txd,
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eth_mdc,
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eth_mdio,
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eth_resetn,
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eth_intn,
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// board gpio
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gpio_bd,
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// lane interface
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rx_ref_clk,
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rx_sysref,
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rx_sync,
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rx_data,
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tx_ref_clk,
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tx_sysref,
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tx_sync,
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tx_data,
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// gpio
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trig,
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adc_fdb,
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adc_fda,
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dac_irq,
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clkd_status,
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adc_pd,
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dac_txen,
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dac_reset,
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clkd_sync,
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// spi
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spi_csn_clk,
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spi_csn_dac,
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spi_csn_adc,
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spi_clk,
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spi_sdio,
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spi_dir);
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// clock and resets
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input sys_clk;
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input sys_resetn;
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// ddr3
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output ddr3_clk_p;
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output ddr3_clk_n;
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output [ 14:0] ddr3_a;
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output [ 2:0] ddr3_ba;
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output ddr3_cke;
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output ddr3_cs_n;
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output ddr3_odt;
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output ddr3_reset_n;
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output ddr3_we_n;
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output ddr3_ras_n;
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output ddr3_cas_n;
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inout [ 7:0] ddr3_dqs_p;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 63:0] ddr3_dq;
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output [ 7:0] ddr3_dm;
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input ddr3_rzq;
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input ddr3_ref_clk;
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// ethernet
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input eth_ref_clk;
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input eth_rxd;
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output eth_txd;
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output eth_mdc;
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inout eth_mdio;
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output eth_resetn;
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input eth_intn;
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// board gpio
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inout [ 26:0] gpio_bd;
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// lane interface
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input rx_ref_clk;
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input rx_sysref;
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output rx_sync;
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input [ 3:0] rx_data;
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input tx_ref_clk;
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input tx_sysref;
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input tx_sync;
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output [ 3:0] tx_data;
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// gpio
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input trig;
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inout adc_fdb;
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inout adc_fda;
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inout dac_irq;
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inout [ 1:0] clkd_status;
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inout adc_pd;
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inout dac_txen;
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inout dac_reset;
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inout clkd_sync;
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// spi
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output spi_csn_clk;
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output spi_csn_dac;
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output spi_csn_adc;
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output spi_clk;
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inout spi_sdio;
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output spi_dir;
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// internal signals
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wire eth_mdio_i;
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wire eth_mdio_o;
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wire eth_mdio_t;
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire spi_miso_s;
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wire spi_mosi_s;
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wire [ 7:0] spi_csn_s;
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wire xcvr_pll_locked;
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wire [ 3:0] xcvr_rx_ready;
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wire [ 3:0] xcvr_tx_ready;
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// daq2
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assign spi_csn_adc = spi_csn_s[2];
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assign spi_csn_dac = spi_csn_s[1];
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assign spi_csn_clk = spi_csn_s[0];
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daq2_spi i_daq2_spi (
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.spi_csn (spi_csn_s[2:0]),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi_s),
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.spi_miso (spi_miso_s),
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.spi_sdio (spi_sdio),
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.spi_dir (spi_dir));
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assign gpio_i[63:60] = xcvr_tx_ready;
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assign gpio_i[59:56] = xcvr_rx_ready;
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assign gpio_i[55:55] = xcvr_pll_locked;
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assign gpio_i[54:44] = 11'd0;
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assign gpio_i[43:43] = trig;
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assign gpio_i[39:39] = 1'd0;
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assign gpio_i[37:37] = 1'd0;
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ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
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.dio_t ({3'h0, 1'h0, 5'h1f}),
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.dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
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.dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
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.dio_p ({ adc_pd, // 42
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dac_txen, // 41
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dac_reset, // 40
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clkd_sync, // 38
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adc_fdb, // 36
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adc_fda, // 35
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dac_irq, // 34
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clkd_status})); // 32
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// board stuff
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assign eth_resetn = 1'b1;
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assign eth_mdio_i = eth_mdio;
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assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
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assign gpio_i[31] = 1'd0;
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assign gpio_i[30] = 1'd0;
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assign gpio_i[29] = 1'd0;
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assign gpio_i[28] = 1'd0;
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assign gpio_i[27] = 1'd0;
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ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
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.dio_t ({11'h7ff, 16'h0}),
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.dio_i (gpio_o[26:0]),
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.dio_o (gpio_i[26:0]),
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.dio_p (gpio_bd));
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system_bd i_system_bd (
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.sys_clk_clk (sys_clk),
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.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
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.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
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.sys_ddr3_cntrl_mem_mem_a (ddr3_a),
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.sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
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.sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
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.sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
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.sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
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.sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
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.sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
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.sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
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.sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
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.sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
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.sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
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.sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
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.sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
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.sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
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.sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
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.sys_ethernet_mdio_mdc (eth_mdc),
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.sys_ethernet_mdio_mdio_in (eth_mdio_i),
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.sys_ethernet_mdio_mdio_out (eth_mdio_o),
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.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
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.sys_ethernet_ref_clk_clk (eth_ref_clk),
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.sys_ethernet_sgmii_rxp_0 (eth_rxd),
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.sys_ethernet_sgmii_txp_0 (eth_txd),
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.sys_gpio_in_port (gpio_i[63:32]),
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.sys_gpio_out_port (gpio_o[63:32]),
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.sys_gpio_bd_in_port (gpio_i[31:0]),
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.sys_gpio_bd_out_port (gpio_o[31:0]),
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.sys_reset_reset_n (sys_resetn),
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.sys_spi_MISO (spi_miso_s),
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.sys_spi_MOSI (spi_mosi_s),
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.sys_spi_SCLK (spi_clk),
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.sys_spi_SS_n (spi_csn_s),
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.sys_xcvr_rstcntrl_pll_locked_pll_locked (xcvr_pll_locked),
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.sys_xcvr_rstcntrl_rx_ready_rx_ready (xcvr_rx_ready),
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.sys_xcvr_rstcntrl_tx_ready_tx_ready (xcvr_tx_ready),
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.sys_xcvr_rx_ref_clk_clk (rx_ref_clk),
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.sys_xcvr_rx_sync_n_export (rx_sync),
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.sys_xcvr_rx_sysref_export (rx_sysref),
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.sys_xcvr_rxd_rx_serial_data (rx_data),
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.sys_xcvr_tx_ref_clk_clk (tx_ref_clk),
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.sys_xcvr_tx_sync_n_export (tx_sync),
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.sys_xcvr_tx_sysref_export (tx_sysref),
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.sys_xcvr_txd_tx_serial_data (tx_data));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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