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There are devices which have a asynchronous data ready signal. (asynchronous with the spi clock) The CDC stages can be enabled by setting up the ASYNC_TRIG parameter. |
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README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects
Branches
Each release has its own branch and master always synced with the latest release. To find out more information about the latest release please check the release notes. Every branch, which has dev in its name, is a development branch and should handle it accordingly.