dd58759cd8
Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain. |
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| .. | ||
| adi_jesd204 | ||
| avl_adxcfg | ||
| avl_adxcvr | ||
| avl_adxcvr_octet_swap | ||
| avl_adxphy | ||
| avl_dacfifo | ||
| axi_adxcvr | ||
| common | ||
| jesd204_phy | ||
| util_clkdiv | ||