edbd9f7b8f
This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select |
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| .. | ||
| Makefile | ||
| avl_adxcfg.v | ||
| avl_adxcfg_hw.tcl | ||