98 lines
2.8 KiB
Verilog
98 lines
2.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module sync_data #(
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parameter NUM_OF_BITS = 1,
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parameter ASYNC_CLK = 1
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) (
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input in_clk,
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input [NUM_OF_BITS-1:0] in_data,
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input out_clk,
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output reg [NUM_OF_BITS-1:0] out_data
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);
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generate
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if (ASYNC_CLK == 1) begin
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wire out_toggle;
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wire in_toggle;
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reg out_toggle_d1 = 1'b0;
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reg in_toggle_d1 = 1'b0;
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reg [NUM_OF_BITS-1:0] cdc_hold;
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sync_bits i_sync_out (
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.in_bits(in_toggle_d1),
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.out_clk(out_clk),
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.out_resetn(1'b1),
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.out_bits(out_toggle)
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);
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sync_bits i_sync_in (
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.in_bits(out_toggle_d1),
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.out_clk(in_clk),
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.out_resetn(1'b1),
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.out_bits(in_toggle)
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);
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wire in_load = in_toggle == in_toggle_d1;
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wire out_load = out_toggle ^ out_toggle_d1;
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always @(posedge in_clk) begin
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if (in_load == 1'b1) begin
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cdc_hold <= in_data;
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in_toggle_d1 <= ~in_toggle_d1;
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end
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end
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always @(posedge out_clk) begin
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if (out_load == 1'b1) begin
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out_data <= cdc_hold;
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end
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out_toggle_d1 <= out_toggle;
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end
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end else begin
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always @(*) begin
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out_data <= in_data;
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end
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end
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endgenerate
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endmodule
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