541 lines
20 KiB
Verilog
541 lines
20 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module avl_dacfifo_rd #(
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parameter AVL_DATA_WIDTH = 512,
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parameter DAC_DATA_WIDTH = 64,
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parameter AVL_BURST_LENGTH = 127,
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parameter AVL_DDR_BASE_ADDRESS = 0,
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parameter AVL_DDR_ADDRESS_LIMIT = 33554432,
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parameter DAC_MEM_ADDRESS_WIDTH = 8)(
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input dac_clk,
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input dac_reset,
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input dac_valid,
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output reg [(DAC_DATA_WIDTH-1):0] dac_data,
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output reg dac_xfer_req,
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output reg dac_dunf,
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input avl_clk,
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input avl_reset,
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output reg [24:0] avl_address,
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output reg [ 6:0] avl_burstcount,
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output [63:0] avl_byteenable,
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input avl_waitrequest,
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input avl_readdatavalid,
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output reg avl_read,
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input [AVL_DATA_WIDTH-1:0] avl_data,
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input [24:0] avl_last_address,
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input [ 6:0] avl_last_burstcount,
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input [ 7:0] dma_last_beats,
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input avl_xfer_req_in,
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output reg avl_xfer_req_out);
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// Max supported MEM_RATIO is 16
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localparam MEM_RATIO = AVL_DATA_WIDTH/DAC_DATA_WIDTH;
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localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_MEM_ADDRESS_WIDTH :
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(MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH - 1) :
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(MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH - 2) :
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(MEM_RATIO == 8) ? (DAC_MEM_ADDRESS_WIDTH - 3) :
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(MEM_RATIO == 16) ? (DAC_MEM_ADDRESS_WIDTH - 4) :
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(DAC_MEM_ADDRESS_WIDTH - 5);
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localparam AVL_MEM_THRESHOLD_LO = AVL_BURST_LENGTH;
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localparam AVL_MEM_THRESHOLD_HI = {(AVL_MEM_ADDRESS_WIDTH){1'b1}} - AVL_BURST_LENGTH;
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localparam DAC_MEM_THRESHOLD = 2 * (AVL_BURST_LENGTH * MEM_RATIO);
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localparam MEM_WIDTH_DIFF = (MEM_RATIO > 16) ? 5 :
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(MEM_RATIO > 8) ? 4 :
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(MEM_RATIO > 4) ? 3 :
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(MEM_RATIO > 2) ? 2 :
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(MEM_RATIO > 1) ? 1 : 1;
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// FSM state definition
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localparam IDLE = 5'b00001;
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localparam XFER_STAGING = 5'b00010;
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localparam XFER_FULL_BURST = 5'b00100;
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localparam XFER_PARTIAL_BURST = 5'b01000;
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localparam XFER_END = 5'b10000;
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// internal register
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_laddr;
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reg avl_mem_laddr_toggle;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_g;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_m1;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_m2;
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reg avl_mem_request_data;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_addr_diff;
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reg [ 4:0] avl_read_state;
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reg [ 7:0] avl_burstcounter;
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reg avl_inread;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_m1;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_m2;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_laddr;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_raddr;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_raddr_g;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_addr_diff;
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reg [ 7:0] dac_mem_laddr_waddr;
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reg [ 7:0] dac_mem_laddr_raddr;
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reg dac_mem_laddr_valid;
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reg dac_avl_xfer_req;
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reg dac_avl_xfer_req_m1;
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reg dac_avl_xfer_req_m2;
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reg [ 7:0] dac_dma_last_beats_m1;
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reg [ 7:0] dac_dma_last_beats_m2;
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reg [ 7:0] dac_dma_last_beats;
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reg [ 3:0] dac_mem_laddr_toggle_m;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_laddr_b;
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reg dac_mem_renable;
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reg dac_mem_valid;
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reg dac_xfer_req_d;
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// internal signals
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wire avl_fifo_reset_s;
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wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_s;
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wire [AVL_MEM_ADDRESS_WIDTH:0] avl_mem_addr_diff_s;
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wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_b2g_s;
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wire [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_g2b_s;
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wire [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_laddr_s;
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wire avl_read_int_s;
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wire avl_end_of_burst_s;
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wire dac_fifo_reset_s;
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wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_addr_diff_s;
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wire [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_s;
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wire [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_g2b_s;
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wire [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_raddr_b2g_s;
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wire [DAC_DATA_WIDTH-1:0] dac_mem_data_s;
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wire dac_mem_laddr_wea_s;
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wire dac_mem_laddr_rea_s;
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wire dac_mem_laddr_unf_s;
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wire [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_laddr_s;
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wire dac_mem_dunf_s;
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// An asymmetric memory to transfer data from Avalon interface to DAC
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// interface
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alt_mem_asym_rd i_mem_asym (
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.mem_i_wrclock (avl_clk),
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.mem_i_wren (avl_readdatavalid),
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.mem_i_wraddress (avl_mem_waddr),
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.mem_i_datain (avl_data),
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.mem_i_rdclock (dac_clk),
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.mem_i_rdaddress (dac_mem_raddr),
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.mem_o_dataout (dac_mem_data_s));
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// the fifo reset is the dma_xfer_req
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assign avl_fifo_reset_s = avl_reset || ~avl_xfer_req_out;
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assign dac_fifo_reset_s = dac_reset || ~dac_avl_xfer_req;
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// loop back the avl_xfer_req to the WRITE module -- this way we can make
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// sure, that in case of a new DMA transfer, the last avalon read burst is
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// finished, so the upcomming avalon writes will not block the interface
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always @(posedge avl_clk) begin
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if (avl_reset == 1'b1) begin
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avl_xfer_req_out <= 1'b0;
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end else begin
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if ((avl_read_state == IDLE) ||
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(avl_read_state == XFER_STAGING) ||
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(avl_read_state == XFER_END)) begin
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avl_xfer_req_out <= avl_xfer_req_in;
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end
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end
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end
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// FSM to generate the necessary Avalon Write transactions
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always @(posedge avl_clk) begin
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if (avl_fifo_reset_s == 1'b1) begin
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avl_read_state <= IDLE;
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avl_burstcount <= AVL_BURST_LENGTH;
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end else begin
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case (avl_read_state)
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IDLE : begin
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if (avl_xfer_req_in == 1'b1) begin
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avl_read_state <= XFER_STAGING;
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end else begin
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avl_read_state <= IDLE;
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end
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end
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XFER_STAGING : begin
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if (avl_xfer_req_in == 1'b1) begin
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if (avl_mem_request_data == 1'b1) begin
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if (avl_address + AVL_BURST_LENGTH <= avl_last_address) begin
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avl_read_state <= XFER_FULL_BURST;
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avl_burstcount <= AVL_BURST_LENGTH;
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end else begin
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avl_read_state <= XFER_PARTIAL_BURST;
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avl_burstcount <= avl_last_burstcount;
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end
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end
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end else begin
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avl_read_state <= IDLE;
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end
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end
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// Avalon transaction with full burst length
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XFER_FULL_BURST : begin
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if (avl_burstcounter < avl_burstcount) begin
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avl_read_state <= XFER_FULL_BURST;
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end else begin
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avl_read_state <= XFER_STAGING;
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end
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end
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// Avalon transaction with the remaining data, burst length is less than
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// the maximum supported burst length
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XFER_PARTIAL_BURST : begin
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if (avl_burstcounter < avl_burstcount) begin
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avl_read_state <= XFER_PARTIAL_BURST;
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end else begin
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avl_read_state <= XFER_END;
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end
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end
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XFER_END : begin
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avl_read_state <= IDLE;
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end
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default : begin
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avl_read_state <= IDLE;
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end
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endcase
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end
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end
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// FSM outputs
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assign avl_read_int_s = ((avl_read_state == XFER_FULL_BURST) ||
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(avl_read_state == XFER_PARTIAL_BURST)) ? 1 : 0;
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assign avl_end_of_burst_s = (avl_burstcount == avl_burstcounter) ? 1 : 0;
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// Avalon address generation and read control signaling
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always @(posedge avl_clk) begin
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if (avl_fifo_reset_s == 1'b1) begin
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avl_address <= AVL_DDR_BASE_ADDRESS;
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end else begin
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if (avl_end_of_burst_s == 1'b1) begin
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avl_address <= (avl_address < avl_last_address) ? avl_address + avl_burstcount : AVL_DDR_BASE_ADDRESS;
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end
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end
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end
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always @(posedge avl_clk) begin
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if (avl_reset == 1'b1) begin
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avl_read <= 1'b0;
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avl_inread <= 1'b0;
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end else begin
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if (avl_read == 1'b0) begin
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if ((avl_waitrequest == 1'b0) && (avl_read_int_s == 1'b1) && (avl_inread == 1'b0)) begin
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avl_read <= 1'b1;
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avl_inread <= 1'b1;
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end
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end else if ((avl_read == 1'b1) && (avl_waitrequest == 1'b0)) begin
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avl_read <= 1'b0;
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end
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if (avl_end_of_burst_s == 1'b1) begin
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avl_inread <= 1'b0;
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end
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end
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end
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// Avalon burstcounter
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always @(posedge avl_clk) begin
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if (avl_fifo_reset_s == 1'b1) begin
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avl_burstcounter <= 8'b0;
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end else begin
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if ((avl_read_int_s == 1'b1) && (avl_readdatavalid == 1'b1)) begin
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avl_burstcounter <= (avl_burstcounter < avl_burstcount) ? avl_burstcounter + 1'b1 : 1'b0;
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end else if (avl_end_of_burst_s == 1'b1) begin
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avl_burstcounter <= 8'b0;
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end
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end
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end
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assign avl_byteenable = {64{1'b1}};
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// write data from Avalon interface into the async FIFO
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always @(posedge avl_clk) begin
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if (avl_fifo_reset_s == 1'b1) begin
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avl_mem_waddr <= 'b0;
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avl_mem_waddr_g <= 'b0;
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avl_mem_laddr <= 'b0;
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avl_mem_laddr_toggle <= 1'b0;
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end else begin
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if (avl_readdatavalid == 1'b1) begin
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avl_mem_waddr <= avl_mem_waddr + 1'b1;
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end
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if (avl_read_state == XFER_END) begin
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avl_mem_laddr <= avl_mem_waddr - 1'b1;
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avl_mem_laddr_toggle <= ~avl_mem_laddr_toggle;
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end
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avl_mem_waddr_g <= avl_mem_waddr_b2g_s;
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end
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end
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ad_b2g #(
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.DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH)
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) i_avl_mem_wr_addr_b2g (
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.din (avl_mem_waddr),
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.dout (avl_mem_waddr_b2g_s));
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// control the FIFO to prevent overflow, underflow is monitored
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assign avl_mem_raddr_s = (MEM_RATIO == 1) ? avl_mem_raddr :
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(MEM_RATIO == 2) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):1] :
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(MEM_RATIO == 4) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):2] :
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(MEM_RATIO == 8) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):3] :
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(MEM_RATIO == 16) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):4] :
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avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):5];
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assign avl_mem_laddr_s = (MEM_RATIO == 1) ? avl_mem_laddr :
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(MEM_RATIO == 2) ? {avl_mem_laddr, 1'b0} :
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(MEM_RATIO == 4) ? {avl_mem_laddr, 2'b0} :
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(MEM_RATIO == 8) ? {avl_mem_laddr, 3'b0} :
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(MEM_RATIO == 16) ? {avl_mem_laddr, 4'b0} :
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{avl_mem_laddr, 5'b0};
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assign avl_mem_addr_diff_s = {1'b1, avl_mem_waddr} - avl_mem_raddr_s;
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always @(posedge avl_clk) begin
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if (avl_fifo_reset_s == 1'b1) begin
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avl_mem_addr_diff <= 'd0;
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avl_mem_raddr <= 'd0;
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avl_mem_raddr_m1 <= 'd0;
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avl_mem_raddr_m2 <= 'd0;
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avl_mem_request_data <= 'd0;
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end else begin
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avl_mem_raddr_m1 <= dac_mem_raddr_g;
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avl_mem_raddr_m2 <= avl_mem_raddr_m1;
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avl_mem_raddr <= avl_mem_raddr_g2b_s;
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avl_mem_addr_diff <= avl_mem_addr_diff_s[AVL_MEM_ADDRESS_WIDTH-1:0];
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if (avl_xfer_req_out == 1'b0) begin
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avl_mem_request_data <= 1'b0;
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end else if (avl_mem_addr_diff >= AVL_MEM_THRESHOLD_HI) begin
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avl_mem_request_data <= 1'b0;
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end else if (avl_mem_addr_diff <= AVL_MEM_THRESHOLD_LO) begin
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avl_mem_request_data <= 1'b1;
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end
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end
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end
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ad_g2b #(
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.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
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) i_avl_mem_rd_addr_g2b (
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.din (avl_mem_raddr_m2),
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.dout (avl_mem_raddr_g2b_s));
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// Push data from the async FIFO to the DAC
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// Data flow is controlled by the DAC, no back-pressure. If FIFO is not
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// ready, data will be dropped
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assign dac_mem_waddr_s = (MEM_RATIO == 1) ? dac_mem_waddr :
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(MEM_RATIO == 2) ? {dac_mem_waddr, 1'b0} :
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(MEM_RATIO == 4) ? {dac_mem_waddr, 2'b0} :
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(MEM_RATIO == 8) ? {dac_mem_waddr, 3'b0} :
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(MEM_RATIO == 16) ? {dac_mem_waddr, 4'b0} :
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{dac_mem_waddr, 5'b0};
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assign dac_mem_addr_diff_s = {1'b1, dac_mem_waddr_s} - dac_mem_raddr;
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always @(posedge dac_clk) begin
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if (dac_fifo_reset_s == 1'b1) begin
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dac_mem_waddr_m2 <= 0;
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dac_mem_waddr_m1 <= 0;
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dac_mem_waddr <= 0;
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dac_mem_laddr <= 0;
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dac_mem_laddr_toggle_m <= 4'b0;
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end else begin
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dac_mem_waddr_m1 <= avl_mem_waddr_g;
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dac_mem_waddr_m2 <= dac_mem_waddr_m1;
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dac_mem_waddr <= dac_mem_waddr_g2b_s;
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dac_mem_laddr_toggle_m <= {dac_mem_laddr_toggle_m[2:0], avl_mem_laddr_toggle};
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dac_mem_laddr <= (dac_mem_laddr_toggle_m[2] ^ dac_mem_laddr_toggle_m[1]) ?
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avl_mem_laddr_s :
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dac_mem_laddr;
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end
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end
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// A buffer for storing the dac_mem_laddr (the address of the last avalon
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// beat inside the CDC fifo)
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// If the stored data sequence is smaller, it can happen that multiple
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// dac_mem_laddr values exist in the same time. This buffers stores this
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// values and make sure that they are feeded to the read logic in order.
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assign dac_mem_laddr_wea_s = dac_mem_laddr_toggle_m[3] ^ dac_mem_laddr_toggle_m[2];
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assign dac_mem_laddr_rea_s = ((dac_mem_raddr == dac_mem_laddr_b) &&
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(dac_mem_laddr_unf_s == 1'b0)) ? 1'b1 :1'b0;
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always @(posedge dac_clk) begin
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if (dac_fifo_reset_s == 1'b1) begin
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dac_mem_laddr_waddr <= 0;
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dac_mem_laddr_raddr <= 0;
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end else begin
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dac_mem_laddr_waddr <= (dac_mem_laddr_wea_s == 1'b1) ? dac_mem_laddr_waddr + 1 : dac_mem_laddr_waddr;
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dac_mem_laddr_raddr <= (dac_mem_laddr_rea_s == 1'b1) ? dac_mem_laddr_raddr + 1 : dac_mem_laddr_raddr;
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end
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end
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assign dac_mem_laddr_unf_s = (dac_mem_laddr_waddr == dac_mem_laddr_raddr) ? 1'b1 : 1'b0;
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always @(posedge dac_clk) begin
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if (dac_fifo_reset_s == 1'b1) begin
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dac_mem_laddr_valid <= 1'b0;
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end else begin
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if (dac_mem_laddr_wea_s == 1'b1)
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dac_mem_laddr_valid <= 1'b1;
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end
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end
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ad_mem #(
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.DATA_WIDTH (DAC_MEM_ADDRESS_WIDTH),
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.ADDRESS_WIDTH (8))
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i_mem (
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.clka (dac_clk),
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.wea (dac_mem_laddr_wea_s),
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.addra (dac_mem_laddr_waddr),
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.dina (dac_mem_laddr),
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.clkb (dac_clk),
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.reb (1'b1),
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.addrb (dac_mem_laddr_raddr),
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.doutb (dac_mem_laddr_s));
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ad_g2b #(
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.DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH)
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) i_dac_mem_wr_addr_g2b (
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.din (dac_mem_waddr_m2),
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.dout (dac_mem_waddr_g2b_s));
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always @(posedge dac_clk) begin
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if (dac_reset == 1'b1) begin
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dac_avl_xfer_req_m2 <= 0;
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dac_avl_xfer_req_m1 <= 0;
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dac_avl_xfer_req <= 0;
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end else begin
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dac_avl_xfer_req_m1 <= avl_xfer_req_out;
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dac_avl_xfer_req_m2 <= dac_avl_xfer_req_m1;
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dac_avl_xfer_req <= dac_avl_xfer_req_m2;
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end
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end
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always @(posedge dac_clk) begin
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if (dac_reset == 1'b1) begin
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dac_dma_last_beats_m2 <= 0;
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dac_dma_last_beats_m1 <= 0;
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dac_dma_last_beats <= 0;
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end else begin
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dac_dma_last_beats_m1 <= dma_last_beats;
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dac_dma_last_beats_m2 <= dac_dma_last_beats_m1;
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dac_dma_last_beats <= dac_dma_last_beats_m2;
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end
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end
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always @(posedge dac_clk) begin
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if (dac_fifo_reset_s == 1'b1) begin
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dac_mem_renable <= 1'b0;
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dac_mem_valid <= 1'b0;
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end else begin
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if (dac_mem_dunf_s == 1'b1) begin
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dac_mem_renable <= 1'b0;
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end else if (dac_mem_addr_diff >= DAC_MEM_THRESHOLD) begin
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dac_mem_renable <= 1'b1;
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end
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dac_mem_valid <= (dac_mem_renable) ? dac_valid : 1'b0;
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end
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end
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assign dac_mem_dunf_s = (dac_mem_addr_diff_s[DAC_MEM_ADDRESS_WIDTH-1:0] == {DAC_MEM_ADDRESS_WIDTH{1'b0}}) ? 1'b1 : 1'b0;
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always @(posedge dac_clk) begin
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if (dac_fifo_reset_s == 1'b1) begin
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dac_mem_raddr <= 0;
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dac_mem_raddr_g <= 0;
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dac_mem_addr_diff <= 0;
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dac_mem_laddr_b <= 0;
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end else begin
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dac_mem_laddr_b <= (!dac_mem_laddr_unf_s) ? dac_mem_laddr_s : dac_mem_laddr_b;
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dac_mem_addr_diff <= dac_mem_addr_diff_s[DAC_MEM_ADDRESS_WIDTH-1:0];
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if (dac_mem_valid) begin
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if ((dac_dma_last_beats != {MEM_WIDTH_DIFF{1'b1}}) &&
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(dac_mem_raddr == (dac_mem_laddr_b + dac_dma_last_beats)) &&
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(dac_mem_laddr_valid == 1'b1)) begin
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dac_mem_raddr <= dac_mem_raddr + (MEM_RATIO - dac_dma_last_beats);
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end else begin
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dac_mem_raddr <= dac_mem_raddr + 1'b1;
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end
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end
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dac_mem_raddr_g <= dac_mem_raddr_b2g_s;
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end
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end
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ad_b2g #(
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.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
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) i_dac_mem_rd_addr_b2g (
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.din (dac_mem_raddr),
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.dout (dac_mem_raddr_b2g_s));
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always @(posedge dac_clk) begin
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if (dac_fifo_reset_s == 1'b1) begin
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dac_xfer_req <= 1'b0;
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dac_xfer_req_d <= 1'b0;
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dac_data <= {DAC_DATA_WIDTH{1'b0}};
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end else begin
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dac_xfer_req_d <= dac_mem_renable;
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dac_xfer_req <= dac_xfer_req_d;
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dac_data <= (dac_xfer_req_d == 1'b1) ? dac_mem_data_s : {DAC_DATA_WIDTH{1'b0}};
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end
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end
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always @(posedge dac_clk) begin
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if (dac_fifo_reset_s == 1'b1) begin
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dac_dunf <= 1'b0;
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end else begin
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dac_dunf <= (dac_mem_addr_diff == 0) ? 1'b1 : 1'b0;
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end
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end
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endmodule
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