Adrian Costina c32b4b02f3 sync_bits: Change I/O names of wires "in" and "out" for VHDL users		2019-04-23 18:03:23 +03:00
..
axi_spi_engine	all: Drive undriven input signals, complete interface	2018-08-10 17:00:11 +03:00
interfaces	spi_engine: Add support for 8 SDI lines	2018-04-11 15:09:54 +03:00
spi_engine_execution	Add missing timescale annotations	2018-10-17 10:32:47 +03:00
spi_engine_interconnect	Add missing timescale annotations	2018-10-17 10:32:47 +03:00
spi_engine_offload	sync_bits: Change I/O names of wires "in" and "out" for VHDL users	2019-04-23 18:03:23 +03:00