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Lars-Peter Clausen 3c5e53ec12 ad_ip_jesd204_tpl_dac: Add Platform Designer presets 
Most converters refer to their different operating modes as a "Mode X"
(where X is a number) in their datasheet. Each mode has a specific framer
configuration associated with it.

Provide a set of Platform Designer (previously known as Qsys) preset files
for each mode. This allows to quickly select a specific operating mode
without having to lookup the corresponding framer configuration from the
datasheet.

A preset can be selected either in the Platform Designer GUI or from a tcl
script using the apply_preset command. E.g.

  add_instance ad9172_transport ad_ip_jesd204_tpl_dac
  apply_preset ad9172_transport "AD9172 Mode 10"

The preset files are generated using the scripts/generate_presets.py
script and the scripts/modes.txt file.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2018-08-23 18:35:30 +03:00
library ad_ip_jesd204_tpl_dac: Add Platform Designer presets 2018-08-23 18:35:30 +03:00
projects daq3: ZCU102: Remove Offload FIFO for ADC path. 2018-08-23 18:06:32 +03:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
LICENSE license: GPL must be GPL v2 2017-05-31 18:18:45 +03:00
LICENSE_ADIBSD license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_GPL2 license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_LGPL license: Add top level license files 2017-05-29 09:57:39 +03:00
Makefile Add quiet mode to the Makefile system 2018-04-11 15:09:54 +03:00
README.md README: Remove the Documentation section, it's redundant 2018-03-07 12:28:40 +00:00
quiet.mk quiet.mk: Fix newline generation in error message 2018-04-12 18:19:43 +02:00

README.md

HDL Reference Designs

Analog Devices Inc. HDL libraries and projects.

Getting started

This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.

Prerequisites

or

Please make sure that you have the required tool version.

How to build a project

For building a projects, you have to use the GNU Make tool. If you're a Windows user please checkout this page, to see how you can install this tool.

To build a project, checkout the latest release, after that just cd to the project that you want to build and run make:

 [~]cd projects/fmcomms2/zc706
 [~]make

A more comprehensive build guide can be found under the following link: https://wiki.analog.com/resources/fpga/docs/build

Software

In general all the projects have no-OS (baremetal) and a Linux support. See no-OS or Linux for more information.

Which branch should I use?

  • If you want to use the most stable code base, always use the latest release branch.

  • If you want to use the greatest and latest, check out the master branch.

License

In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.

The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.

See LICENSE for more details. The separate license files cab be found here:

Comprehensive user guide

See HDL User Guide for a more detailed guide.

Support

Feel free to ask any question at EngineerZone.