242 lines
7.3 KiB
Verilog
242 lines
7.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9152 (
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// jesd interface
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// tx_clk is (line-rate/40)
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tx_clk,
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tx_data,
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// dma interface
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dac_clk,
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dac_valid_0,
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dac_enable_0,
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dac_ddata_0,
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dac_valid_1,
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dac_enable_1,
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dac_ddata_1,
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dac_dovf,
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dac_dunf,
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rdata,
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s_axi_rresp,
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s_axi_rready);
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// parameters
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parameter PCORE_ID = 0;
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parameter PCORE_DAC_DP_DISABLE = 0;
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// jesd interface
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// tx_clk is (line-rate/40)
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input tx_clk;
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output [127:0] tx_data;
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// dma interface
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output dac_clk;
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output dac_valid_0;
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output dac_enable_0;
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input [ 63:0] dac_ddata_0;
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output dac_valid_1;
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output dac_enable_1;
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input [ 63:0] dac_ddata_1;
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input dac_dovf;
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input dac_dunf;
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [ 31:0] s_axi_awaddr;
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output s_axi_awready;
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input s_axi_wvalid;
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input [ 31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [ 31:0] s_axi_araddr;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 31:0] s_axi_rdata;
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output [ 1:0] s_axi_rresp;
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input s_axi_rready;
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// internal clocks and resets
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wire dac_rst;
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wire up_clk;
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wire up_rstn;
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// internal signals
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wire [ 15:0] dac_data_0_0_s;
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wire [ 15:0] dac_data_0_1_s;
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wire [ 15:0] dac_data_0_2_s;
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wire [ 15:0] dac_data_0_3_s;
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wire [ 15:0] dac_data_1_0_s;
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wire [ 15:0] dac_data_1_1_s;
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wire [ 15:0] dac_data_1_2_s;
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wire [ 15:0] dac_data_1_3_s;
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wire up_wreq_s;
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wire [ 13:0] up_waddr_s;
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wire [ 31:0] up_wdata_s;
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wire up_wack_s;
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wire up_rreq_s;
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wire [ 13:0] up_raddr_s;
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wire [ 31:0] up_rdata_s;
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wire up_rack_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// device interface
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axi_ad9152_if i_if (
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.tx_clk (tx_clk),
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.tx_data (tx_data),
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data_0_0 (dac_data_0_0_s),
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.dac_data_0_1 (dac_data_0_1_s),
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.dac_data_0_2 (dac_data_0_2_s),
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.dac_data_0_3 (dac_data_0_3_s),
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.dac_data_1_0 (dac_data_1_0_s),
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.dac_data_1_1 (dac_data_1_1_s),
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.dac_data_1_2 (dac_data_1_2_s),
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.dac_data_1_3 (dac_data_1_3_s));
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// core
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axi_ad9152_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data_0_0 (dac_data_0_0_s),
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.dac_data_0_1 (dac_data_0_1_s),
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.dac_data_0_2 (dac_data_0_2_s),
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.dac_data_0_3 (dac_data_0_3_s),
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.dac_data_1_0 (dac_data_1_0_s),
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.dac_data_1_1 (dac_data_1_1_s),
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.dac_data_1_2 (dac_data_1_2_s),
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.dac_data_1_3 (dac_data_1_3_s),
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.dac_valid_0 (dac_valid_0),
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.dac_enable_0 (dac_enable_0),
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.dac_ddata_0 (dac_ddata_0),
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.dac_valid_1 (dac_valid_1),
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.dac_enable_1 (dac_enable_1),
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.dac_ddata_1 (dac_ddata_1),
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.dac_dovf (dac_dovf),
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.dac_dunf (dac_dunf),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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