3d8e05ac17
The clock monitor reports the ratio of the clock frequencies of a known reference clock and a monitored unknown clock. The frequency ratio is reported in a 16.16 fixed-point format. This means that it is possible to detect clocks that are 65535 times faster than the reference clock. For a reference clock of 100 MHz that is 6.5 THz and even if the reference clock is running at only 1 MHz it is still 65 GHz, a clock rate much faster than what we'd ever expect in a FPGA. Add a configuration option to the clock monitor that allows to reduce the number of integer bits of ratio. This allows to reduce the utilization while still being able to cover all realistic clock frequencies. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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