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Lars-Peter Clausen 3d8e05ac17 up_clock_mon: Make counter width configurable 
The clock monitor reports the ratio of the clock frequencies of a known
reference clock and a monitored unknown clock. The frequency ratio is
reported in a 16.16 fixed-point format.

This means that it is possible to detect clocks that are 65535 times faster
than the reference clock. For a reference clock of 100 MHz that is 6.5 THz
and even if the reference clock is running at only 1 MHz it is still 65
GHz, a clock rate much faster than what we'd ever expect in a FPGA.

Add a configuration option to the clock monitor that allows to reduce the
number of integer bits of ratio. This allows to reduce the utilization
while still being able to cover all realistic clock frequencies.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-05-23 11:16:07 +02:00
..
altera alt_mul- qsys replacement 2017-05-18 10:38:48 -04:00
axi_ad5766 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad6676 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad7616 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9122 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9144 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9152 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9162 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9234 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9250 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9265 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9361 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9371 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9434 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9467 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9625 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9643 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9652 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9671 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9680 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9684 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9739a all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9963 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_adc_decimate all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_adc_trigger all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_clkgen all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_dac_interpolate all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_dmac all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_fmcadc5_sync all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_generic_adc all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_gpreg all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_hdmi_rx axi_hdmi_rx- move data to an iob 2017-05-19 16:25:54 -04:00
axi_hdmi_tx all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_i2s_adi license: Fix VHDL license header 2017-05-17 18:28:06 +03:00
axi_intr_monitor all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_logic_analyzer all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_mc_controller all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_mc_current_monitor all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_mc_speed all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_rd_wr_combiner all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_spdif_rx license: Fix VHDL license header 2017-05-17 18:28:06 +03:00
axi_spdif_tx Fix VHDL files license header, second try 2017-05-17 15:25:08 +02:00
axi_usb_fx3 axi_usb_fx3: Add missing ports 2017-05-17 14:48:28 +03:00
cn0363 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
common up_clock_mon: Make counter width configurable 2017-05-23 11:16:07 +02:00
cordic_demod all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
interfaces interfaces: Add dependencies to rule 2017-05-23 11:16:07 +02:00
prcfg all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
scripts adi-ip-alt allow changing device family 2017-05-17 16:13:26 -04:00
spi_engine all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_adcfifo resolving conflicts 2017-05-17 16:18:53 -04:00
util_axis_fifo all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_axis_resize all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_bsplit all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_ccat all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_cic all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_clkdiv all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_cpack all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_dacfifo all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_extract all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_fir_dec all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_fir_int all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_gmii_to_rgmii all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_i2c_mixer Fix VHDL files license header, second try 2017-05-17 15:25:08 +02:00
util_mfifo all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_pmod_adc all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_pmod_fmeter all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_pulse_gen util_pulse_gen: Add Makefile 2017-04-27 11:28:25 +03:00
util_rfifo all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_sigma_delta_spi all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_tdd_sync all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_upack all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_var_fifo all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_wfifo all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
xilinx up_clock_mon: Remove extra hold register 2017-05-23 11:16:07 +02:00
Makefile library: Sort Makefile 2017-05-19 15:33:26 +02:00