281 lines
7.4 KiB
VHDL
281 lines
7.4 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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--
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-- Each core or library found in this collection may have its own licensing terms.
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-- The user should keep this in in mind while exploring these cores.
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--
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-- Redistribution and use in source and binary forms,
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-- with or without modification of this file, are permitted under the terms of either
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-- (at the option of the user):
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--
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-- 1. The GNU General Public License version 2 as published by the
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-- Free Software Foundation, which can be found in the top level directory, or at:
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-- https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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--
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-- OR
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--
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-- 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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-- https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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--
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.fifo_synchronizer;
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use work.i2s_clkgen;
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use work.i2s_tx;
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use work.i2s_rx;
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entity i2s_controller is
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generic(
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C_SLOT_WIDTH : integer := 24; -- Width of one Slot
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C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
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C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
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C_NUM_CH : integer := 1;
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C_HAS_TX : integer := 1;
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C_HAS_RX : integer := 1
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);
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port(
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clk : in std_logic; -- System clock
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resetn : in std_logic; -- System reset
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data_clk : in std_logic; -- Data clock should be less than clk / 4
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bclk_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock
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lrclk_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock
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sdata_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output
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sdata_i : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input
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tx_enable : in Boolean; -- Enable TX
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tx_ack : out std_logic; -- Request new Slot Data
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tx_stb : in std_logic; -- Request new Slot Data
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tx_data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
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rx_enable : in Boolean; -- Enable RX
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rx_ack : in std_logic;
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rx_stb : out std_logic; -- Valid Slot Data
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rx_data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
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-- Runtime parameter
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bclk_div_rate : in natural range 0 to 255;
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lrclk_div_rate : in natural range 0 to 255
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);
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end i2s_controller;
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architecture Behavioral of i2s_controller is
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constant NUM_TX : integer := C_HAS_TX * C_NUM_CH;
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constant NUM_RX : integer := C_HAS_RX * C_NUM_CH;
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signal enable : Boolean;
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signal cdc_sync_stage0_tick : std_logic;
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signal cdc_sync_stage1_tick : std_logic;
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signal cdc_sync_stage2_tick : std_logic;
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signal cdc_sync_stage3_tick : std_logic;
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signal BCLK_O_int : std_logic;
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signal LRCLK_O_int : std_logic;
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signal tx_bclk : std_logic;
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signal tx_lrclk : std_logic;
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signal tx_sdata : std_logic_vector(C_NUM_CH - 1 downto 0);
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signal tx_tick : std_logic;
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signal tx_channel_sync : std_logic;
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signal tx_frame_sync : std_logic;
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signal const_1 : std_logic;
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signal bclk_tick : std_logic;
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signal rx_bclk : std_logic;
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signal rx_lrclk : std_logic;
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signal rx_sdata : std_logic_vector(NUM_RX - 1 downto 0);
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signal rx_channel_sync : std_logic;
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signal rx_frame_sync : std_logic;
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signal tx_sync_fifo_out : std_logic_vector(3 + NUM_TX downto 0);
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signal tx_sync_fifo_in : std_logic_vector(3 + NUM_TX downto 0);
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signal rx_sync_fifo_out : std_logic_vector(3 + NUM_RX downto 0);
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signal rx_sync_fifo_in : std_logic_vector(3 + NUM_RX downto 0);
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signal data_resetn : std_logic;
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signal data_reset_vec : std_logic_vector(2 downto 0);
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begin
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enable <= rx_enable or tx_enable;
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const_1 <= '1';
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process (data_clk, resetn)
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begin
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if resetn = '0' then
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data_reset_vec <= (others => '1');
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elsif rising_edge(data_clk) then
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data_reset_vec(2 downto 1) <= data_reset_vec(1 downto 0);
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data_reset_vec(0) <= '0';
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end if;
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end process;
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data_resetn <= not data_reset_vec(2);
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-- Generate tick signal in the DATA_CLK_I domain
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process (data_clk)
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begin
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if rising_edge(data_clk) then
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cdc_sync_stage0_tick <= not cdc_sync_stage0_tick;
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end if;
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end process;
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process (clk)
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begin
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if rising_edge(clk) then
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cdc_sync_stage1_tick <= cdc_sync_stage0_tick;
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cdc_sync_stage2_tick <= cdc_sync_stage1_tick;
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cdc_sync_stage3_tick <= cdc_sync_stage2_tick;
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end if;
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end process;
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tx_tick <= cdc_sync_stage2_tick xor cdc_sync_stage3_tick;
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tx_sync_fifo_in(0) <= tx_channel_sync;
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tx_sync_fifo_in(1) <= tx_frame_sync;
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tx_sync_fifo_in(2) <= tx_bclk;
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tx_sync_fifo_in(3) <= tx_lrclk;
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tx_sync_fifo_in(3 + NUM_TX downto 4) <= tx_sdata;
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process (data_clk)
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begin
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if rising_edge(data_clk) then
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if data_resetn = '0' then
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bclk_o <= (others => '1');
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lrclk_o <= (others => '1');
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sdata_o <= (others => '0');
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else
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if C_BCLK_POL = 0 then
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bclk_o <= (others => tx_sync_fifo_out(2));
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else
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bclk_o <= (others => not tx_sync_fifo_out(2));
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end if;
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if C_LRCLK_POL = 0 then
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lrclk_o <= (others => tx_sync_fifo_out(3));
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else
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lrclk_o <= (others => not tx_sync_fifo_out(3));
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end if;
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if C_HAS_TX = 1 then
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sdata_o <= tx_sync_fifo_out(3 + NUM_TX downto 4);
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end if;
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if C_HAS_RX = 1 then
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rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0);
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rx_sync_fifo_in(3 + NUM_RX downto 4) <= sdata_i;
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end if;
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end if;
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end if;
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end process;
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tx_sync: entity fifo_synchronizer
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generic map (
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DEPTH => 4,
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WIDTH => NUM_TX + 4
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)
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port map (
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in_resetn => resetn,
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in_clk => clk,
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in_data => tx_sync_fifo_in,
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in_tick => tx_tick,
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out_resetn => data_resetn,
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out_clk => data_clk,
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out_data => tx_sync_fifo_out
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);
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clkgen: entity i2s_clkgen
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port map(
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clk => clk,
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resetn => resetn,
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enable => enable,
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tick => tx_tick,
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bclk_div_rate => bclk_div_rate,
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lrclk_div_rate => lrclk_div_rate,
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channel_sync => tx_channel_sync,
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frame_sync => tx_frame_sync,
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bclk => tx_bclk,
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lrclk => tx_lrclk
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);
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tx_gen: if C_HAS_TX = 1 generate
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tx: entity i2s_tx
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generic map (
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C_SLOT_WIDTH => C_SLOT_WIDTH,
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C_NUM => NUM_TX
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)
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port map (
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clk => clk,
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resetn => resetn,
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enable => tx_enable,
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channel_sync => tx_channel_sync,
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frame_sync => tx_frame_sync,
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bclk => tx_bclk,
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sdata => tx_sdata,
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ack => tx_ack,
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stb => tx_stb,
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data => tx_data
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);
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end generate;
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rx_gen: if C_HAS_RX = 1 generate
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rx: entity i2s_rx
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generic map (
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C_SLOT_WIDTH => C_SLOT_WIDTH,
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C_NUM => NUM_RX
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)
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port map (
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clk => clk,
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resetn => resetn,
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enable => rx_enable,
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channel_sync => rx_channel_sync,
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frame_sync => rx_frame_sync,
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bclk => rx_bclk,
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sdata => rx_sdata,
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ack => rx_ack,
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stb => rx_stb,
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data => rx_data
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);
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rx_channel_sync <= rx_sync_fifo_out(0);
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rx_frame_sync <= rx_sync_fifo_out(1);
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rx_bclk <= rx_sync_fifo_out(2);
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rx_lrclk <= rx_sync_fifo_out(3);
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rx_sdata <= rx_sync_fifo_out(3 + NUM_RX downto 4);
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rx_sync: entity fifo_synchronizer
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generic map (
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DEPTH => 4,
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WIDTH => NUM_RX + 4
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)
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port map (
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in_resetn => data_resetn,
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in_clk => data_clk,
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in_data => rx_sync_fifo_in,
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in_tick => const_1,
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out_resetn => resetn,
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out_clk => clk,
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out_data => rx_sync_fifo_out
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);
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end generate;
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end Behavioral;
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