90 lines
2.5 KiB
Verilog
90 lines
2.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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// Color Space Conversion, multiplier. This is a simple partial product adder
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// that generates the product of the two inputs.
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`timescale 1ps/1ps
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module ad_csc_1_mul #(
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parameter DELAY_DATA_WIDTH = 16) (
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// data_a is signed
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input clk,
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input [16:0] data_a,
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input [ 7:0] data_b,
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output [24:0] data_p,
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// delay match
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input [DW:0] ddata_in,
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output reg [DW:0] ddata_out);
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localparam DW = DELAY_DATA_WIDTH - 1;
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// internal registers
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reg [DW:0] p1_ddata = 'd0;
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reg [DW:0] p2_ddata = 'd0;
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reg p1_sign = 'd0;
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reg p2_sign = 'd0;
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reg sign_p = 'd0;
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// internal signals
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wire [25:0] data_p_s;
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// a/b reg, m-reg, p-reg delay match
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always @(posedge clk) begin
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p1_ddata <= ddata_in;
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p2_ddata <= p1_ddata;
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ddata_out <= p2_ddata;
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end
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always @(posedge clk) begin
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p1_sign <= data_a[16];
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p2_sign <= p1_sign;
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sign_p <= p2_sign;
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end
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assign data_p = {sign_p, data_p_s[23:0]};
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MULT_MACRO #(
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.LATENCY (3),
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.WIDTH_A (17),
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.WIDTH_B (9))
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i_mult_macro (
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.CE (1'b1),
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.RST (1'b0),
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.CLK (clk),
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.A ({1'b0, data_a[15:0]}),
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.B ({1'b0, data_b}),
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.P (data_p_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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