100 lines
3.2 KiB
Verilog
100 lines
3.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_xcvr_rx_if #(
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parameter DEVICE_TYPE = 0) (
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// jesd interface
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input rx_clk,
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input [ 3:0] rx_ip_sof,
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input [31:0] rx_ip_data,
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output reg rx_sof,
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output reg [31:0] rx_data);
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// internal registers
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reg [31:0] rx_ip_data_d = 'd0;
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reg [ 3:0] rx_ip_sof_hold = 'd0;
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reg rx_ip_sof_d = 'd0;
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// internal signals
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wire [ 3:0] rx_ip_sof_s;
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wire [31:0] rx_ip_data_s;
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// altera/xilinx
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generate
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if (DEVICE_TYPE == 1) begin
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assign rx_ip_sof_s[3] = rx_ip_sof[0];
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assign rx_ip_sof_s[2] = rx_ip_sof[1];
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assign rx_ip_sof_s[1] = rx_ip_sof[2];
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assign rx_ip_sof_s[0] = rx_ip_sof[3];
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assign rx_ip_data_s[31:24] = rx_ip_data[ 7: 0];
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assign rx_ip_data_s[23:16] = rx_ip_data[15: 8];
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assign rx_ip_data_s[15: 8] = rx_ip_data[23:16];
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assign rx_ip_data_s[ 7: 0] = rx_ip_data[31:24];
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end else begin
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assign rx_ip_sof_s[3] = rx_ip_sof[3];
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assign rx_ip_sof_s[2] = rx_ip_sof[2];
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assign rx_ip_sof_s[1] = rx_ip_sof[1];
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assign rx_ip_sof_s[0] = rx_ip_sof[0];
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assign rx_ip_data_s[31:24] = rx_ip_data[31:24];
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assign rx_ip_data_s[23:16] = rx_ip_data[23:16];
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assign rx_ip_data_s[15: 8] = rx_ip_data[15: 8];
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assign rx_ip_data_s[ 7: 0] = rx_ip_data[ 7: 0];
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end
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endgenerate
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// dword may contain more than one frame per clock
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always @(posedge rx_clk) begin
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rx_ip_data_d <= rx_ip_data_s;
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rx_ip_sof_d <= rx_ip_sof_s;
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if (rx_ip_sof_s != 4'h0) begin
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rx_ip_sof_hold <= rx_ip_sof_s;
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end
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rx_sof <= |rx_ip_sof_d;
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if (rx_ip_sof_hold[0] == 1'b1) begin
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rx_data <= rx_ip_data_s;
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end else if (rx_ip_sof_hold[1] == 1'b1) begin
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rx_data <= {rx_ip_data_s[ 7:0], rx_ip_data_d[31: 8]};
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end else if (rx_ip_sof_hold[2] == 1'b1) begin
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rx_data <= {rx_ip_data_s[15:0], rx_ip_data_d[31:16]};
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end else if (rx_ip_sof_hold[3] == 1'b1) begin
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rx_data <= {rx_ip_data_s[23:0], rx_ip_data_d[31:24]};
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end else begin
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rx_data <= 32'd0;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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