pluto_hdl_adi/library/axi_dmac/tb
Istvan Csomortani 157afcbc33 tb_base: Fix various test benches
The tb_base.v verilog files does not contain a full module definition,
just some plain test code. In general the files is sourced inside the
test bench main module. As is, defining a timescale in these files will
generate an error, because timescale directive can not be inside a
module.

Delete all the timescale directive from these files.
2019-05-17 11:20:48 +03:00
..
axi_read_slave.v axi_dmac: tb: Allow testing asymmetric interface widths 2018-11-30 23:41:49 +02:00
axi_slave.v axi_dmac: tb: Allow testing asymmetric interface widths 2018-11-30 23:41:49 +02:00
axi_write_slave.v axi_dmac: tb: Allow testing asymmetric interface widths 2018-11-30 23:41:49 +02:00
dma_read_shutdown_tb axi_dmac: burst_memory: Add support for using asymmetric memory 2018-11-30 23:41:49 +02:00
dma_read_shutdown_tb.v axi_dmac: burst_memory: Consider DMA_LENGTH_ALIGN 2018-11-30 23:41:49 +02:00
dma_read_tb axi_dmac: burst_memory: Add support for using asymmetric memory 2018-11-30 23:41:49 +02:00
dma_read_tb.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
dma_write_shutdown_tb axi_dmac: burst_memory: Add support for using asymmetric memory 2018-11-30 23:41:49 +02:00
dma_write_shutdown_tb.v axi_dmac: burst_memory: Consider DMA_LENGTH_ALIGN 2018-11-30 23:41:49 +02:00
dma_write_tb axi_dmac: burst_memory: Add support for using asymmetric memory 2018-11-30 23:41:49 +02:00
dma_write_tb.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
regmap_tb axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
regmap_tb.v axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
reset_manager_tb axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
reset_manager_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
run_tb.sh axi_dmac/tb: Add support for xsim 2018-11-07 12:13:06 +02:00
tb_base.v tb_base: Fix various test benches 2019-05-17 11:20:48 +03:00