136 lines
4.0 KiB
Verilog
Executable File
136 lines
4.0 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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module axi_sysid #(
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parameter ROM_WIDTH = 32,
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parameter ROM_ADDR_BITS = 9)(
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//axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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input [ROM_WIDTH-1:0] sys_rom_data,
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input [ROM_WIDTH-1:0] pr_rom_data,
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output [ROM_ADDR_BITS-1:0] rom_addr);
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localparam AXI_ADDRESS_WIDTH = 12;
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localparam [31:0] CORE_VERSION = {16'h0001, /* MAJOR */
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8'h00, /* MINOR */
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8'h61}; /* PATCH */
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localparam [31:0] CORE_MAGIC = 32'h53594944; // SYID
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reg up_wack = 'd0;
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reg [31:0] up_rdata_s = 'd0;
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reg up_rack_s = 'd0;
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reg up_rreq_s_d = 'd0;
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reg [31:0] up_scratch = 'd0;
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wire up_clk;
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wire up_rstn;
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wire up_rreq_s;
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wire [(ROM_ADDR_BITS+1):0] up_raddr_s;
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wire up_wreq_s;
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wire [(ROM_ADDR_BITS+1):0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] rom_data_s;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign rom_addr = up_raddr_s [ROM_ADDR_BITS-1:0];
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assign rom_data_s = (up_raddr_s [ROM_ADDR_BITS + 1'h1: ROM_ADDR_BITS] == 2'h1) ? sys_rom_data :
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(up_raddr_s [ROM_ADDR_BITS + 1'h1: ROM_ADDR_BITS] == 2'h2) ? pr_rom_data : 'h0;
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up_axi #(
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.AXI_ADDRESS_WIDTH(ROM_ADDR_BITS+4))
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i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr[ROM_ADDR_BITS+3:0]),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr[ROM_ADDR_BITS+3:0]),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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//delaying data read with 1 tck to compensate for the ROM latency
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always @(posedge up_clk) begin
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up_rreq_s_d <= up_rreq_s;
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end
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//axi registers read
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_rack_s <= 'd0;
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up_rdata_s <= 'd0;
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end else begin
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up_rack_s <= up_rreq_s_d;
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if (up_rreq_s_d == 1'b1) begin
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case (up_raddr_s)
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8'h00: up_rdata_s <= CORE_VERSION;
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8'h01: up_rdata_s <= 0;
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8'h02: up_rdata_s <= up_scratch;
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8'h03: up_rdata_s <= CORE_MAGIC;
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8'h10: up_rdata_s <= ROM_ADDR_BITS;
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default: begin
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up_rdata_s <= rom_data_s;
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end
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endcase
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end else begin
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up_rdata_s <= 32'd0;
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end
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end
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end
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//axi registers write
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin
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up_scratch <= up_wdata_s;
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end
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end
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end
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endmodule
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