566 lines
18 KiB
Verilog
Executable File
566 lines
18 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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sys_clk,
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// hps
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ddr3_a,
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ddr3_ba,
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ddr3_ck_p,
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ddr3_ck_n,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_ras_n,
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ddr3_cas_n,
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ddr3_we_n,
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ddr3_reset_n,
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ddr3_dq,
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ddr3_dqs_p,
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ddr3_dqs_n,
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ddr3_odt,
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ddr3_dm,
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ddr3_oct_rzqin,
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eth1_tx_clk,
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eth1_tx_ctl,
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eth1_txd0,
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eth1_txd1,
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eth1_txd2,
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eth1_txd3,
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eth1_rx_clk,
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eth1_rx_ctl,
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eth1_rxd0,
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eth1_rxd1,
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eth1_rxd2,
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eth1_rxd3,
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eth1_mdc,
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eth1_mdio,
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qspi_ss0,
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qspi_clk,
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qspi_io0,
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qspi_io1,
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qspi_io2,
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qspi_io3,
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sdio_clk,
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sdio_cmd,
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sdio_d0,
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sdio_d1,
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sdio_d2,
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sdio_d3,
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usb1_clk,
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usb1_stp,
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usb1_dir,
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usb1_nxt,
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usb1_d0,
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usb1_d1,
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usb1_d2,
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usb1_d3,
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usb1_d4,
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usb1_d5,
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usb1_d6,
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usb1_d7,
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uart0_rx,
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uart0_tx,
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uart1_rx,
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uart1_tx,
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i2c0_scl,
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i2c0_sda,
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trace_clk,
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trace_d0,
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trace_d1,
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trace_d2,
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trace_d3,
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trace_d4,
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trace_d5,
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trace_d6,
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trace_d7,
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gpio_gpio00,
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gpio_gpio17,
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gpio_gpio18,
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gpio_gpio22,
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gpio_gpio24,
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gpio_gpio26,
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gpio_gpio27,
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gpio_gpio35,
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gpio_gpio40,
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gpio_gpio41,
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gpio_gpio42,
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gpio_gpio43,
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// board gpio
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led,
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push_buttons,
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dip_switches,
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// hdmi
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hdmi_out_clk,
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hdmi_data,
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// lane interface
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ref_clk,
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rx_data,
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rx_sync,
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rx_sysref,
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// spi
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spi_csn,
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spi_clk,
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spi_sdio);
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// clock and resets
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input sys_clk;
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// hps
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output [ 14:0] ddr3_a;
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output [ 2:0] ddr3_ba;
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output ddr3_ck_p;
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output ddr3_ck_n;
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output ddr3_cke;
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output ddr3_cs_n;
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output ddr3_ras_n;
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output ddr3_cas_n;
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output ddr3_we_n;
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output ddr3_reset_n;
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inout [ 39:0] ddr3_dq;
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inout [ 4:0] ddr3_dqs_p;
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inout [ 4:0] ddr3_dqs_n;
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output ddr3_odt;
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output [ 4:0] ddr3_dm;
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input ddr3_oct_rzqin;
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output eth1_tx_clk;
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output eth1_tx_ctl;
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output eth1_txd0;
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output eth1_txd1;
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output eth1_txd2;
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output eth1_txd3;
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input eth1_rx_clk;
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input eth1_rx_ctl;
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input eth1_rxd0;
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input eth1_rxd1;
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input eth1_rxd2;
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input eth1_rxd3;
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output eth1_mdc;
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inout eth1_mdio;
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output qspi_ss0;
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output qspi_clk;
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inout qspi_io0;
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inout qspi_io1;
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inout qspi_io2;
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inout qspi_io3;
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output sdio_clk;
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inout sdio_cmd;
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inout sdio_d0;
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inout sdio_d1;
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inout sdio_d2;
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inout sdio_d3;
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input usb1_clk;
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output usb1_stp;
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input usb1_dir;
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input usb1_nxt;
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inout usb1_d0;
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inout usb1_d1;
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inout usb1_d2;
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inout usb1_d3;
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inout usb1_d4;
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inout usb1_d5;
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inout usb1_d6;
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inout usb1_d7;
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input uart0_rx;
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output uart0_tx;
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input uart1_rx;
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output uart1_tx;
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inout i2c0_scl;
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inout i2c0_sda;
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output trace_clk;
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output trace_d0;
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output trace_d1;
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output trace_d2;
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output trace_d3;
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output trace_d4;
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output trace_d5;
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output trace_d6;
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output trace_d7;
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inout gpio_gpio00;
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inout gpio_gpio17;
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inout gpio_gpio18;
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inout gpio_gpio22;
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inout gpio_gpio24;
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inout gpio_gpio26;
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inout gpio_gpio27;
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inout gpio_gpio35;
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inout gpio_gpio40;
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inout gpio_gpio41;
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inout gpio_gpio42;
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inout gpio_gpio43;
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// board gpio
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output [ 3:0] led;
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input [ 3:0] push_buttons;
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input [ 3:0] dip_switches;
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// hdmi
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output hdmi_out_clk;
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output [ 3:0] hdmi_data;
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// lane interface
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input ref_clk;
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input [ 3:0] rx_data;
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output rx_sync;
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output rx_sysref;
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// spi
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output spi_csn;
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output spi_clk;
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inout spi_sdio;
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// internal registers
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reg rx_sysref_m1 = 'd0;
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reg rx_sysref_m2 = 'd0;
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reg rx_sysref_m3 = 'd0;
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reg rx_sysref = 'd0;
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reg [ 63:0] sys_hdmi_pll_reconfig_in = 'd0;
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reg [ 63:0] sys_hdmi_pll_reconfig_reconfig_in = 'd0;
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// internal clocks and resets
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wire sys_resetn;
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wire rx_clk;
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wire adc0_clk;
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wire adc1_clk;
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// internal signals
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wire sys_pll_locked_s;
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wire spi_csn_s;
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wire spi_clk_s;
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wire spi_mosi_s;
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wire spi_miso_s;
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wire [ 63:0] adc0_ddata_s;
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wire adc0_dsync_s;
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wire adc0_dovf_s;
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wire adc0_dwr_s;
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wire adc0_mon_valid_s;
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wire [ 55:0] adc0_mon_data_s;
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wire [ 63:0] adc1_ddata_s;
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wire adc1_dsync_s;
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wire adc1_dovf_s;
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wire adc1_dwr_s;
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wire adc1_mon_valid_s;
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wire [ 55:0] adc1_mon_data_s;
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wire [ 3:0] rx_ip_sof_s;
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wire [127:0] rx_ip_data_s;
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wire [127:0] rx_data_s;
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wire rx_sw_rstn_s;
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wire rx_sysref_s;
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wire rx_err_s;
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wire rx_ready_s;
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wire [ 3:0] rx_rst_state_s;
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wire rx_lane_aligned_s;
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wire [ 3:0] rx_analog_reset_s;
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wire [ 3:0] rx_digital_reset_s;
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wire [ 3:0] rx_cdr_locked_s;
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wire [ 3:0] rx_cal_busy_s;
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wire rx_pll_locked_s;
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wire [ 15:0] rx_xcvr_status_s;
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wire [ 63:0] sys_hdmi_pll_reconfig_out;
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wire [ 63:0] sys_hdmi_pll_reconfig_reconfig_out;
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// instantiations
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always @(posedge rx_clk) begin
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rx_sysref_m1 <= rx_sysref_s;
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rx_sysref_m2 <= rx_sysref_m1;
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rx_sysref_m3 <= rx_sysref_m2;
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rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
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end
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sld_signaltap #(
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.sld_advanced_trigger_entity ("basic,1,"),
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.sld_data_bits (114),
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.sld_data_bit_cntr_bits (8),
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.sld_enable_advanced_trigger (0),
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.sld_mem_address_bits (10),
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.sld_node_crc_bits (32),
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.sld_node_crc_hiword (10311),
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.sld_node_crc_loword (14297),
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.sld_node_info (1076736),
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.sld_ram_block_type ("AUTO"),
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.sld_sample_depth (1024),
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.sld_storage_qualifier_gap_record (0),
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.sld_storage_qualifier_mode ("OFF"),
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.sld_trigger_bits (2),
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.sld_trigger_in_enabled (0),
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.sld_trigger_level (1),
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.sld_trigger_level_pipeline (1))
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i_signaltap (
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.acq_clk (rx_clk),
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.acq_data_in ({rx_sysref, rx_sync, adc1_mon_data_s, adc0_mon_data_s}),
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.acq_trigger_in ({rx_sysref, rx_sync}));
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genvar n;
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generate
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for (n = 0; n < 4; n = n + 1) begin: g_align_1
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ad_jesd_align i_jesd_align (
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.rx_clk (rx_clk),
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.rx_sof (rx_ip_sof_s),
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.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
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.rx_data (rx_data_s[n*32+31:n*32]));
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end
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endgenerate
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assign rx_xcvr_status_s[15:15] = 1'd0;
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assign rx_xcvr_status_s[14:14] = rx_sync;
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assign rx_xcvr_status_s[13:13] = rx_ready_s;
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assign rx_xcvr_status_s[12:12] = rx_pll_locked_s;
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assign rx_xcvr_status_s[11: 8] = rx_rst_state_s;
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assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s;
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assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s;
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ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst (
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.rx_clk (rx_clk),
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.rx_rstn (sys_resetn),
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.rx_sw_rstn (rx_sw_rstn_s),
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.rx_pll_locked (rx_pll_locked_s),
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.rx_cal_busy (rx_cal_busy_s),
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.rx_cdr_locked (rx_cdr_locked_s),
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.rx_analog_reset (rx_analog_reset_s),
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.rx_digital_reset (rx_digital_reset_s),
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.rx_ready (rx_ready_s),
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.rx_rst_state (rx_rst_state_s));
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fmcjesdadc1_spi i_fmcjesdadc1_spi (
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.sys_clk (sys_clk),
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.spi4_csn (spi_csn_s),
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.spi4_clk (spi_clk_s),
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.spi4_mosi (spi_mosi_s),
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.spi4_miso (spi_miso_s),
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.spi3_csn (spi_csn),
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.spi3_clk (spi_clk),
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.spi3_sdio (spi_sdio));
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// pipe line to fix timing
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always @(posedge sys_clk) begin
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sys_hdmi_pll_reconfig_in <= sys_hdmi_pll_reconfig_reconfig_out;
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sys_hdmi_pll_reconfig_reconfig_in <= sys_hdmi_pll_reconfig_out;
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end
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system_bd i_system_bd (
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.memory_mem_a (ddr3_a),
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.memory_mem_ba (ddr3_ba),
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.memory_mem_ck (ddr3_ck_p),
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.memory_mem_ck_n (ddr3_ck_n),
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.memory_mem_cke (ddr3_cke),
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.memory_mem_cs_n (ddr3_cs_n),
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.memory_mem_ras_n (ddr3_ras_n),
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.memory_mem_cas_n (ddr3_cas_n),
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.memory_mem_we_n (ddr3_we_n),
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.memory_mem_reset_n (ddr3_reset_n),
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.memory_mem_dq (ddr3_dq),
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.memory_mem_dqs (ddr3_dqs_p),
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.memory_mem_dqs_n (ddr3_dqs_n),
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.memory_mem_odt (ddr3_odt),
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.memory_mem_dm (ddr3_dm),
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.memory_oct_rzqin (ddr3_oct_rzqin),
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.clk_clk (sys_clk),
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.reset_reset_n (sys_resetn),
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.axi_ad9250_0_xcvr_clk_clk (rx_clk),
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.axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]),
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.axi_ad9250_0_adc_clock_clk (adc0_clk),
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.axi_ad9250_0_adc_dma_if_ddata (adc0_ddata_s),
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.axi_ad9250_0_adc_dma_if_dsync (adc0_dsync_s),
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.axi_ad9250_0_adc_dma_if_dovf (adc0_dovf_s),
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.axi_ad9250_0_adc_dma_if_dunf (1'b0),
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.axi_ad9250_0_adc_dma_if_dwr (adc0_dwr_s),
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.axi_ad9250_0_adc_mon_if_valid (adc0_mon_valid_s),
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.axi_ad9250_0_adc_mon_if_data (adc0_mon_data_s),
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.axi_dmac_0_fifo_wr_clock_clk (adc0_clk),
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.axi_dmac_0_fifo_wr_if_ovf (adc0_dovf_s),
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.axi_dmac_0_fifo_wr_if_wren (adc0_dwr_s),
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.axi_dmac_0_fifo_wr_if_data (adc0_ddata_s),
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.axi_dmac_0_fifo_wr_if_sync (adc0_dsync_s),
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.axi_ad9250_1_xcvr_clk_clk (rx_clk),
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.axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]),
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.axi_ad9250_1_adc_clock_clk (adc1_clk),
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.axi_ad9250_1_adc_dma_if_ddata (adc1_ddata_s),
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.axi_ad9250_1_adc_dma_if_dsync (adc1_dsync_s),
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.axi_ad9250_1_adc_dma_if_dovf (adc1_dovf_s),
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.axi_ad9250_1_adc_dma_if_dunf (1'b0),
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.axi_ad9250_1_adc_dma_if_dwr (adc1_dwr_s),
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.axi_ad9250_1_adc_mon_if_valid (adc1_mon_valid_s),
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.axi_ad9250_1_adc_mon_if_data (adc1_mon_data_s),
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.axi_dmac_1_fifo_wr_clock_clk (adc1_clk),
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.axi_dmac_1_fifo_wr_if_ovf (adc1_dovf_s),
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.axi_dmac_1_fifo_wr_if_wren (adc1_dwr_s),
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.axi_dmac_1_fifo_wr_if_data (adc1_ddata_s),
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.axi_dmac_1_fifo_wr_if_sync (adc1_dsync_s),
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.sys_jesd204b_s1_ref_clk_in_clk_clk (ref_clk),
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.sys_jesd204b_s1_rx_clk_out_clk_clk (rx_clk),
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.sys_jesd204b_s1_jesd204_rx_link_data (rx_ip_data_s),
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.sys_jesd204b_s1_jesd204_rx_link_valid (),
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.sys_jesd204b_s1_jesd204_rx_link_ready (1'b1),
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.sys_jesd204b_s1_alldev_lane_aligned_export (rx_lane_aligned_s),
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.sys_jesd204b_s1_sysref_export (rx_sysref),
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|
.sys_jesd204b_s1_jesd204_rx_frame_error_export (rx_err_s),
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.sys_jesd204b_s1_dev_lane_aligned_export (rx_lane_aligned_s),
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|
.sys_jesd204b_s1_dev_sync_n_export (rx_sync),
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|
.sys_jesd204b_s1_sof_export (rx_ip_sof_s),
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|
.sys_jesd204b_s1_rx_serial_data_rx_serial_data (rx_data),
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|
.sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
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|
.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
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|
.sys_jesd204b_s1_rx_islockedtodata_export (rx_cdr_locked_s),
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|
.sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s),
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|
.sys_hps_spim0_txd (spi_mosi_s),
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|
.sys_hps_spim0_rxd (spi_miso_s),
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|
.sys_hps_spim0_ss_in_n (1'b1),
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|
.sys_hps_spim0_ssi_oe_n (),
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|
.sys_hps_spim0_ss_0_n (spi_csn_s),
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|
.sys_hps_spim0_ss_1_n (),
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|
.sys_hps_spim0_ss_2_n (),
|
|
.sys_hps_spim0_ss_3_n (),
|
|
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
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|
.sys_hps_spim0_sclk_out_clk (spi_clk_s),
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|
.sys_hps_f2h_stm_hw_events_stm_hwevents ({16'd0, led, push_buttons, dip_switches}),
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|
.hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
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|
.hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
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|
.hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
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|
.hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
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|
.hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
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|
.hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
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|
.hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
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|
.hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
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|
.hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
|
|
.hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
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|
.hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
|
|
.hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
|
|
.hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
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|
.hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
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|
.hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
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|
.hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
|
|
.hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
|
|
.hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
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|
.hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
|
|
.hps_io_hps_io_qspi_inst_CLK (qspi_clk),
|
|
.hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
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|
.hps_io_hps_io_sdio_inst_D0 (sdio_d0),
|
|
.hps_io_hps_io_sdio_inst_D1 (sdio_d1),
|
|
.hps_io_hps_io_sdio_inst_CLK (sdio_clk),
|
|
.hps_io_hps_io_sdio_inst_D2 (sdio_d2),
|
|
.hps_io_hps_io_sdio_inst_D3 (sdio_d3),
|
|
.hps_io_hps_io_usb1_inst_D0 (usb1_d0),
|
|
.hps_io_hps_io_usb1_inst_D1 (usb1_d1),
|
|
.hps_io_hps_io_usb1_inst_D2 (usb1_d2),
|
|
.hps_io_hps_io_usb1_inst_D3 (usb1_d3),
|
|
.hps_io_hps_io_usb1_inst_D4 (usb1_d4),
|
|
.hps_io_hps_io_usb1_inst_D5 (usb1_d5),
|
|
.hps_io_hps_io_usb1_inst_D6 (usb1_d6),
|
|
.hps_io_hps_io_usb1_inst_D7 (usb1_d7),
|
|
.hps_io_hps_io_usb1_inst_CLK (usb1_clk),
|
|
.hps_io_hps_io_usb1_inst_STP (usb1_stp),
|
|
.hps_io_hps_io_usb1_inst_DIR (usb1_dir),
|
|
.hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
|
|
.hps_io_hps_io_uart0_inst_RX (uart0_rx),
|
|
.hps_io_hps_io_uart0_inst_TX (uart0_tx),
|
|
.hps_io_hps_io_uart1_inst_RX (uart1_rx),
|
|
.hps_io_hps_io_uart1_inst_TX (uart1_tx),
|
|
.hps_io_hps_io_i2c0_inst_SDA (i2c0_sda),
|
|
.hps_io_hps_io_i2c0_inst_SCL (i2c0_scl),
|
|
.hps_io_hps_io_trace_inst_CLK (trace_clk),
|
|
.hps_io_hps_io_trace_inst_D0 (trace_d0),
|
|
.hps_io_hps_io_trace_inst_D1 (trace_d1),
|
|
.hps_io_hps_io_trace_inst_D2 (trace_d2),
|
|
.hps_io_hps_io_trace_inst_D3 (trace_d3),
|
|
.hps_io_hps_io_trace_inst_D4 (trace_d4),
|
|
.hps_io_hps_io_trace_inst_D5 (trace_d5),
|
|
.hps_io_hps_io_trace_inst_D6 (trace_d6),
|
|
.hps_io_hps_io_trace_inst_D7 (trace_d7),
|
|
.hps_io_hps_io_gpio_inst_GPIO00 (gpio_gpio00),
|
|
.hps_io_hps_io_gpio_inst_GPIO17 (gpio_gpio17),
|
|
.hps_io_hps_io_gpio_inst_GPIO18 (gpio_gpio18),
|
|
.hps_io_hps_io_gpio_inst_GPIO22 (gpio_gpio22),
|
|
.hps_io_hps_io_gpio_inst_GPIO24 (gpio_gpio24),
|
|
.hps_io_hps_io_gpio_inst_GPIO26 (gpio_gpio26),
|
|
.hps_io_hps_io_gpio_inst_GPIO27 (gpio_gpio27),
|
|
.hps_io_hps_io_gpio_inst_GPIO35 (gpio_gpio35),
|
|
.hps_io_hps_io_gpio_inst_GPIO40 (gpio_gpio40),
|
|
.hps_io_hps_io_gpio_inst_GPIO41 (gpio_gpio41),
|
|
.hps_io_hps_io_gpio_inst_GPIO42 (gpio_gpio42),
|
|
.hps_io_hps_io_gpio_inst_GPIO43 (gpio_gpio43),
|
|
.sys_hps_h2f_reset_reset_n (sys_resetn),
|
|
.sys_gpio_external_connection_in_port ({rx_xcvr_status_s, 4'd0, push_buttons, 4'd0, dip_switches}),
|
|
.sys_gpio_external_connection_out_port ({14'd0, rx_sw_rstn_s, rx_sysref_s, 12'd0, led}),
|
|
.axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk),
|
|
.axi_hdmi_tx_0_hdmi_if_h16_hsync (),
|
|
.axi_hdmi_tx_0_hdmi_if_h16_vsync (),
|
|
.axi_hdmi_tx_0_hdmi_if_h16_data_e (),
|
|
.axi_hdmi_tx_0_hdmi_if_h16_data (),
|
|
.axi_hdmi_tx_0_hdmi_if_h16_es_data (hdmi_data),
|
|
.axi_hdmi_tx_0_hdmi_if_h24_hsync (),
|
|
.axi_hdmi_tx_0_hdmi_if_h24_vsync (),
|
|
.axi_hdmi_tx_0_hdmi_if_h24_data_e (),
|
|
.axi_hdmi_tx_0_hdmi_if_h24_data (),
|
|
.axi_hdmi_tx_0_hdmi_if_h36_hsync (),
|
|
.axi_hdmi_tx_0_hdmi_if_h36_vsync (),
|
|
.axi_hdmi_tx_0_hdmi_if_h36_data_e (),
|
|
.axi_hdmi_tx_0_hdmi_if_h36_data (),
|
|
.sys_hdmi_pll_reconfig_to_pll_reconfig_to_pll (sys_hdmi_pll_reconfig_in),
|
|
.sys_hdmi_pll_reconfig_from_pll_reconfig_from_pll (sys_hdmi_pll_reconfig_out),
|
|
.sys_hdmi_pll_reconfig_reconfig_to_pll_reconfig_to_pll (sys_hdmi_pll_reconfig_reconfig_out),
|
|
.sys_hdmi_pll_reconfig_reconfig_from_pll_reconfig_from_pll (sys_hdmi_pll_reconfig_reconfig_in));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|