136 lines
4.1 KiB
Verilog
136 lines
4.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_register_slice #(
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parameter DATA_WIDTH = 32,
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parameter FORWARD_REGISTERED = 0,
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parameter BACKWARD_REGISTERED = 0
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) (
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input clk,
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input resetn,
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input s_axi_valid,
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output s_axi_ready,
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input [DATA_WIDTH-1:0] s_axi_data,
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output m_axi_valid,
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input m_axi_ready,
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output [DATA_WIDTH-1:0] m_axi_data
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);
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/*
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s_axi_data -> bwd_data -> fwd_data(1) -> m_axi_data
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s_axi_valid -> bwd_valid -> fwd_valid(1) -> m_axi_valid
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s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready
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(1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid
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(2) BACKWARD_REGISTERED insters a FF before s_axi_ready
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*/
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wire [DATA_WIDTH-1:0] bwd_data_s;
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wire bwd_valid_s;
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wire bwd_ready_s;
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wire [DATA_WIDTH-1:0] fwd_data_s;
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wire fwd_valid_s;
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wire fwd_ready_s;
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generate if (FORWARD_REGISTERED == 1) begin
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reg fwd_valid = 1'b0;
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reg [DATA_WIDTH-1:0] fwd_data = 'h00;
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assign fwd_ready_s = ~fwd_valid | m_axi_ready;
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assign fwd_valid_s = fwd_valid;
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assign fwd_data_s = fwd_data;
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always @(posedge clk) begin
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if (~fwd_valid | m_axi_ready)
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fwd_data <= bwd_data_s;
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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fwd_valid <= 1'b0;
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end else begin
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if (bwd_valid_s)
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fwd_valid <= 1'b1;
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else if (m_axi_ready)
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fwd_valid <= 1'b0;
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end
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end
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end else begin
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assign fwd_data_s = bwd_data_s;
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assign fwd_valid_s = bwd_valid_s;
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assign fwd_ready_s = m_axi_ready;
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end
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endgenerate
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generate if (BACKWARD_REGISTERED == 1) begin
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reg bwd_ready = 1'b1;
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reg [DATA_WIDTH-1:0] bwd_data = 'h00;
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assign bwd_valid_s = ~bwd_ready | s_axi_valid;
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assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
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assign bwd_ready_s = bwd_ready;
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always @(posedge clk) begin
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if (bwd_ready)
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bwd_data <= s_axi_data;
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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bwd_ready <= 1'b1;
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end else begin
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if (fwd_ready_s)
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bwd_ready <= 1'b1;
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else if (s_axi_valid)
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bwd_ready <= 1'b0;
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end
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end
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end else begin
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assign bwd_valid_s = s_axi_valid;
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assign bwd_data_s = s_axi_data;
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assign bwd_ready_s = fwd_ready_s;
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end endgenerate
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assign m_axi_data = fwd_data_s;
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assign m_axi_valid = fwd_valid_s;
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assign s_axi_ready = bwd_ready_s;
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endmodule
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