191 lines
6.5 KiB
Verilog
191 lines
6.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dest_axi_mm #(
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parameter ID_WIDTH = 3,
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parameter DMA_DATA_WIDTH = 64,
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parameter DMA_ADDR_WIDTH = 32,
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parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
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parameter BEATS_PER_BURST_WIDTH = 4,
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parameter MAX_BYTES_PER_BURST = 128,
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parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST),
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parameter AXI_LENGTH_WIDTH = 8,
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parameter CACHE_COHERENT = 0
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) (
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input m_axi_aclk,
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input m_axi_aresetn,
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input req_valid,
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output req_ready,
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input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address,
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input bl_valid,
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output bl_ready,
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input [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,
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input enable,
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output enabled,
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output response_valid,
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input response_ready,
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output [1:0] response_resp,
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output response_resp_eot,
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output response_resp_partial,
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output [BYTES_PER_BURST_WIDTH-1:0] response_data_burst_length,
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input [ID_WIDTH-1:0] request_id,
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output [ID_WIDTH-1:0] response_id,
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output [ID_WIDTH-1:0] address_id,
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input address_eot,
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input response_eot,
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input fifo_valid,
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output fifo_ready,
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input [DMA_DATA_WIDTH-1:0] fifo_data,
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input [DMA_DATA_WIDTH/8-1:0] fifo_strb,
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input fifo_last,
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input [BYTES_PER_BURST_WIDTH-1:0] dest_burst_info_length,
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input dest_burst_info_partial,
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input [ID_WIDTH-1:0] dest_burst_info_id,
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input dest_burst_info_write,
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// Write address
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input m_axi_awready,
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output m_axi_awvalid,
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output [DMA_ADDR_WIDTH-1:0] m_axi_awaddr,
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output [AXI_LENGTH_WIDTH-1:0] m_axi_awlen,
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output [ 2:0] m_axi_awsize,
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output [ 1:0] m_axi_awburst,
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output [ 2:0] m_axi_awprot,
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output [ 3:0] m_axi_awcache,
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// Write data
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output [DMA_DATA_WIDTH-1:0] m_axi_wdata,
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output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb,
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input m_axi_wready,
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output m_axi_wvalid,
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output m_axi_wlast,
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// Write response
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input m_axi_bvalid,
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input [ 1:0] m_axi_bresp,
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output m_axi_bready
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);
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wire address_enabled;
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address_generator #(
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.ID_WIDTH(ID_WIDTH),
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.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
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.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
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.DMA_DATA_WIDTH(DMA_DATA_WIDTH),
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.LENGTH_WIDTH(AXI_LENGTH_WIDTH),
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.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
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.CACHE_COHERENT(CACHE_COHERENT)
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) i_addr_gen (
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.clk(m_axi_aclk),
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.resetn(m_axi_aresetn),
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.enable(enable),
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.enabled(address_enabled),
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.id(address_id),
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.request_id(request_id),
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.req_valid(req_valid),
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.req_ready(req_ready),
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.req_address(req_address),
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.bl_valid(bl_valid),
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.bl_ready(bl_ready),
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.measured_last_burst_length(measured_last_burst_length),
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.eot(address_eot),
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.addr_ready(m_axi_awready),
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.addr_valid(m_axi_awvalid),
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.addr(m_axi_awaddr),
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.len(m_axi_awlen),
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.size(m_axi_awsize),
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.burst(m_axi_awburst),
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.prot(m_axi_awprot),
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.cache(m_axi_awcache));
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assign m_axi_wvalid = fifo_valid;
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assign fifo_ready = m_axi_wready;
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assign m_axi_wlast = fifo_last;
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assign m_axi_wdata = fifo_data;
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assign m_axi_wstrb = fifo_strb;
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response_handler #(
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.ID_WIDTH(ID_WIDTH)
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) i_response_handler (
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.clk(m_axi_aclk),
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.resetn(m_axi_aresetn),
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.bvalid(m_axi_bvalid),
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.bready(m_axi_bready),
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.bresp(m_axi_bresp),
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.enable(address_enabled),
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.enabled(enabled),
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.id(response_id),
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.request_id(address_id),
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.eot(response_eot),
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.resp_valid(response_valid),
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.resp_ready(response_ready),
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.resp_resp(response_resp),
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.resp_eot(response_resp_eot));
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reg [BYTES_PER_BURST_WIDTH+1-1:0] bl_mem [0:2**(ID_WIDTH)-1];
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assign {response_resp_partial,
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response_data_burst_length} = bl_mem[response_id];
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always @(posedge m_axi_aclk) begin
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if (dest_burst_info_write) begin
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bl_mem[dest_burst_info_id] <= {dest_burst_info_partial,
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dest_burst_info_length};
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end
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end
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endmodule
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