294 lines
10 KiB
Verilog
Executable File
294 lines
10 KiB
Verilog
Executable File
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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// Limitations:
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// for DATA_PATH_WIDTH = 4, 8
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// F*K=4, multiples of DATA_PATH_WIDTH
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// F=1,2,3,4,6, and multiples of DATA_PATH_WIDTH
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// for DATA_PATH_WIDTH = 6
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// F=3,6
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// for DATA_PATH_WIDTH = 12
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// F=3,6,12
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`timescale 1ns/100ps
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module jesd204_frame_mark #(
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parameter DATA_PATH_WIDTH = 4
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) (
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input clk,
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input reset,
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input [9:0] cfg_octets_per_multiframe,
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input [7:0] cfg_beats_per_multiframe,
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input [7:0] cfg_octets_per_frame,
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output reg [DATA_PATH_WIDTH-1:0] sof,
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output reg [DATA_PATH_WIDTH-1:0] eof,
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output reg [DATA_PATH_WIDTH-1:0] somf,
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output reg [DATA_PATH_WIDTH-1:0] eomf
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);
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localparam MAX_OCTETS_PER_FRAME = 32;
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localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
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localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 :
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MAX_OCTETS_PER_FRAME > 64 ? 7 :
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MAX_OCTETS_PER_FRAME > 32 ? 6 :
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MAX_OCTETS_PER_FRAME > 16 ? 5 :
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MAX_OCTETS_PER_FRAME > 8 ? 4 :
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MAX_OCTETS_PER_FRAME > 4 ? 3 :
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MAX_OCTETS_PER_FRAME > 2 ? 2 : 1;
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localparam BEATS_PER_FRAME_WIDTH = CW-DPW_LOG2;
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localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2;
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// For DATA_PATH_WIDTH = 8, special case if F*K%8=4
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wire octets_per_mf_4_mod_8 = (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2];
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reg [BEATS_PER_MF_WIDTH-1:0] cur_beats_per_multiframe;
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reg mf_phase;
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reg [1:0] beat_cnt_mod_3;
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reg [BEATS_PER_FRAME_WIDTH-1:0] beat_cnt_frame;
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wire cur_sof;
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wire cur_eof;
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reg [BEATS_PER_MF_WIDTH-1:0] beat_cnt_mf;
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wire cur_somf;
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wire cur_eomf;
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wire [DATA_PATH_WIDTH-1:0] default_sof;
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wire [DATA_PATH_WIDTH-1:0] default_eof;
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wire [BEATS_PER_FRAME_WIDTH-1:0] cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2];
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reg [DATA_PATH_WIDTH-1:0] sof_f_3[2:0];
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reg [DATA_PATH_WIDTH-1:0] eof_f_3[2:0];
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reg [DATA_PATH_WIDTH-1:0] sof_f_6[2:0];
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reg [DATA_PATH_WIDTH-1:0] eof_f_6[2:0];
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reg [DATA_PATH_WIDTH-1:0] sof_f_12[2:0];
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reg [DATA_PATH_WIDTH-1:0] eof_f_12[2:0];
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generate
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if(DATA_PATH_WIDTH == 4) begin : gen_dp_4
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initial begin
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sof_f_3[0] = {4'b1001};
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sof_f_3[1] = {4'b0100};
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sof_f_3[2] = {4'b0010};
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eof_f_3[0] = {4'b0100};
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eof_f_3[1] = {4'b0010};
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eof_f_3[2] = {4'b1001};
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sof_f_6[0] = {4'b0001};
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sof_f_6[1] = {4'b0100};
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sof_f_6[2] = {4'b0000};
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eof_f_6[0] = {4'b0000};
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eof_f_6[1] = {4'b0010};
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eof_f_6[2] = {4'b1000};
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end
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end else if(DATA_PATH_WIDTH == 6) begin : gen_dp_6
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initial begin
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sof_f_3[0] = {6'b001001};
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sof_f_3[1] = {6'b001001};
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sof_f_3[2] = {6'b001001};
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eof_f_3[0] = {6'b100100};
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eof_f_3[1] = {6'b100100};
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eof_f_3[2] = {6'b100100};
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sof_f_6[0] = {6'b000001};
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sof_f_6[1] = {6'b000001};
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sof_f_6[2] = {6'b000001};
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eof_f_6[0] = {6'b100000};
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eof_f_6[1] = {6'b100000};
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eof_f_6[2] = {6'b100000};
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end
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end else if(DATA_PATH_WIDTH == 8) begin : gen_dp_8
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initial begin
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sof_f_3[0] = {8'b01001001};
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sof_f_3[1] = {8'b10010010};
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sof_f_3[2] = {8'b00100100};
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eof_f_3[0] = {8'b00100100};
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eof_f_3[1] = {8'b01001001};
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eof_f_3[2] = {8'b10010010};
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sof_f_6[0] = {8'b01000001};
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sof_f_6[1] = {8'b00010000};
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sof_f_6[2] = {8'b00000100};
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eof_f_6[0] = {8'b00100000};
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eof_f_6[1] = {8'b00001000};
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eof_f_6[2] = {8'b10000010};
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sof_f_12[0] = {8'b00000001};
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sof_f_12[1] = {8'b00010000};
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sof_f_12[2] = {8'b00000000};
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eof_f_12[0] = {8'b00000000};
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eof_f_12[1] = {8'b00001000};
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eof_f_12[2] = {8'b10000000};
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end
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end
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// Beat count % 3, to support F=3, 6, 12
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always @(posedge clk) begin
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if(reset) begin
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beat_cnt_mod_3 <= 2'd0;
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end else begin
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if(beat_cnt_mod_3 == 2'd2) begin
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beat_cnt_mod_3 <= 2'd0;
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end else begin
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beat_cnt_mod_3 <= beat_cnt_mod_3 + 1'b1;
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end
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end
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end
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// Beat count per frame
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always @(posedge clk) begin
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if(reset) begin
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beat_cnt_frame <= {BEATS_PER_FRAME_WIDTH{1'b0}};
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end else begin
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if(beat_cnt_frame == cfg_beats_per_frame) begin
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beat_cnt_frame <= {BEATS_PER_FRAME_WIDTH{1'b0}};
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end else begin
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beat_cnt_frame <= beat_cnt_frame + 1'b1;
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end
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end
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end
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assign cur_sof = beat_cnt_frame == 0;
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assign cur_eof = beat_cnt_frame == cfg_beats_per_frame;
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assign default_sof = {{DATA_PATH_WIDTH-1{1'b0}}, cur_sof};
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assign default_eof = {cur_eof, {DATA_PATH_WIDTH-1{1'b0}}};
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// cfg_octets_per_frame must be a multiple of DATA_PATH_WIDTH
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// except for the following supported special cases
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always @(*) begin
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case(cfg_octets_per_frame)
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8'd0:
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begin
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sof = {DATA_PATH_WIDTH{1'b1}};
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eof = {DATA_PATH_WIDTH{1'b1}};
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end
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8'd1:
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begin
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sof = {DATA_PATH_WIDTH/2{2'b01}};
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eof = {DATA_PATH_WIDTH/2{2'b10}};
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end
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8'd2:
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begin
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sof = sof_f_3[beat_cnt_mod_3];
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eof = eof_f_3[beat_cnt_mod_3];
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end
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8'd3:
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begin
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sof = {DATA_PATH_WIDTH/4{4'b0001}};
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eof = {DATA_PATH_WIDTH/4{4'b1000}};
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end
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8'd5:
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begin
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sof = sof_f_6[beat_cnt_mod_3];
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eof = eof_f_6[beat_cnt_mod_3];
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end
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8'd11:
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begin
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sof = (DATA_PATH_WIDTH == 4) ? default_sof : sof_f_12[beat_cnt_mod_3];
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eof = (DATA_PATH_WIDTH == 4) ? default_eof : eof_f_12[beat_cnt_mod_3];
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end
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default:
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begin
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sof = default_sof;
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eof = default_eof;
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end
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endcase
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end
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// Beat count per multiframe
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// Only support F*K%4=0
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// If DATA_PATH_WIDTH == 4, or if DATA_PATH_WIDTH == 8 and F*K%8=0,
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// then multiframes always start/end at the first/last octet in the data bus
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// Otherwise, start/end of multiframe have more complicated patterns
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always @(posedge clk) begin
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if(reset) begin
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beat_cnt_mf <= 8'b0;
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mf_phase <= 1'b0;
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end else begin
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if(beat_cnt_mf == cur_beats_per_multiframe) begin
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beat_cnt_mf <= 8'b0;
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mf_phase <= ~mf_phase;
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end else begin
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beat_cnt_mf <= beat_cnt_mf + 1'b1;
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end
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end
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end
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assign cur_somf = beat_cnt_mf == 0;
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assign cur_eomf = beat_cnt_mf == cur_beats_per_multiframe;
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if(DATA_PATH_WIDTH == 4 || DATA_PATH_WIDTH == 6) begin : gen_mf_dp_4_6
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always @(*) begin
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cur_beats_per_multiframe = cfg_beats_per_multiframe;
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somf = {{DATA_PATH_WIDTH-1{1'b0}}, cur_somf};
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eomf = {cur_eomf, {DATA_PATH_WIDTH-1{1'b0}}};
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end
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end else if(DATA_PATH_WIDTH == 8) begin : gen_mf_dp_8
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always @(*) begin
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// cfg_octets_per_multiframe = 4
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if(cfg_octets_per_multiframe[9:2] == 0) begin
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cur_beats_per_multiframe = 8'hXX;
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somf = 8'h11;
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eomf = 8'h88;
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end else if(~octets_per_mf_4_mod_8) begin
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cur_beats_per_multiframe = cfg_beats_per_multiframe;
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somf = {{DATA_PATH_WIDTH-1{1'b0}}, cur_somf};
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eomf = {cur_eomf, {DATA_PATH_WIDTH-1{1'b0}}};
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end else begin
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cur_beats_per_multiframe = cfg_beats_per_multiframe - mf_phase;
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if((mf_phase == 0) && (beat_cnt_mf == 0)) begin
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somf = 8'h01;
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end else if((mf_phase == 0) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
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somf = 8'h10;
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end else begin
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somf = 8'b0;
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end
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if((mf_phase == 0) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
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eomf = 8'h08;
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end else if((mf_phase == 1) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
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eomf = 8'h80;
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end else begin
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eomf = 8'b0;
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end
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end
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end
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end
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endgenerate
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endmodule
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